Data processing: measuring – calibrating – or testing – Testing system
Reexamination Certificate
1999-05-10
2002-03-19
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
C327S317000
Reexamination Certificate
active
06360180
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a driver having loss compensation circuitry for use in a semiconductor tester to test semiconductor devices.
BACKGROUND OF THE INVENTION
Automatic test equipment often plays a critical role in the manufacturing process for semiconductor devices. The equipment, often referred to as a “tester”, simulates an operating environment for devices at the wafer and package levels. By verifying the operability of each semiconductor device under varying conditions, manufacturers can realize high yields, and a correspondingly higher level of reliability to customers. Not surprisingly, this translates into higher revenues for the semiconductor manufacturer.
Testers employed by semiconductor manufacturers generally include a computer workstation that runs test software for controlling the test. The software controls the signal parameters for test vectors or waveforms that will drive the semiconductor device. A pattern generator typically produces the waveforms and routes the signals to electronic circuits commonly referred to as pin electronics.
The pin electronics generally reside on one or more channel cards that route signals between the tester and one or more pins of the DUT. The pin electronics perform several tester functions and generally serve as a signal interface between the pattern generator and the DUT. One of the more important functions includes driving waveforms along a transmission path to the pins of the (DUT).
With reference to
FIG. 1
, one conventional driver employed in traditional pin electronics channel cards generally comprises a buffer amplifier
10
employed in an integrated circuit that includes respective high and low voltage clamps
12
and
14
to produce respective high VH and low VL voltage levels. A switch
16
selectively couples the buffer output between the voltage clamps according to a pre-programmed timing scheme controlled by the test controller. The switching between the respective clamps forms a substantially squarewave-shaped signal
18
for transmission along a signal path
20
to the DUT (not shown).
One of the problems associated with the conventional driver described above involves the timing accuracy of the actual waveform delivered to the DUT. At frequencies approaching the gigahertz range, the signal driven from the driver output is often subjected to losses arising from impedance mismatching along the transmission path.
FIG. 2
illustrates an affected waveform with an original edge risetime at
22
, and a subsequent degraded risetime at
24
due to skin effect impedance and dielectric losses. Because high frequency testing requires exacting timing parameters to adequately test a DUT, losses affecting edge risetimes and pulse shape, and hence timing accuracy, are often unacceptable to semiconductor manufacturers.
What is needed and heretofore unavailable is a driver for use in a semiconductor tester channel card that pre-compensates for transmission path signal losses to maximize timing accuracy and signal integrity for driver waveforms. The driver of the present invention satisfies this need.
SUMMARY OF THE INVENTION
The driver of the present invention employs pre-compensation circuitry to generate a waveform that, after propagating along a lossy transmission path, takes the form of the originally programmed signal. This allows highly accurate timing at the input pins of a DUT for edges propagating at relatively high frequencies.
To realize the foregoing advantages, the invention in one form comprises a driver for applying a deterministic waveform along a lossy transmission path to a device-under-test. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.
In another form, the invention comprises a channel card for use in a semiconductor tester to drive and capture signals to and from a device-under-test. The channel card includes a formatter and a comparator having an input coupled to the device-under-test and an output feeding the formatter. The channel card further includes a driver having an input coupled to the formatter and an output connected through a lossy transmission path to the device-under-test. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.
In yet another form, the invention comprises a method of applying a driving waveform from a driver output along a lossy signal path to a device-under-test. The method includes the steps of establishing a first clamped signal level; switching the driver output to the first clamped signal level; and injecting energy into the output node to modify the first clamped signal level and compensate for losses to the clamped signal level along the lossy signal path.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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Patent Abstract of Japan vol. 017, No. 295 (E-1377), Jun. 7, 1993 & JP 05 022106A (Toshiba Corp), Jan. 29, 1993 abstract.
Hoff Marc S.
Kreisman Lance M.
Pretlow Demetrius
Teradyne, Inc.
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