Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-05-26
2003-04-22
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000
Reexamination Certificate
active
06552710
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver unit for driving an active matrix LCD device in a dot reversible driving scheme and, more particularly, to a structure of the horizontal driver in the driver unit.
2. Description of the Related Art
Active matrix LCD devices are now used in a variety of applications due to their advantages of light weight, low operating voltage, low power dissipation and small thickness.
FIG. 1
shows a conventional active matrix LCD module including a drive unit
200
in a dot reversible driving scheme.
The LCD panel
100
includes front and rear panels sandwiching therebetween liquid crystal. The rear panel has a plurality of pixel elements arranged in a matrix and each including a TFT (thin film transistor) and a pixel electrode, whereas the front panel has a common electrode and color filters. The rear panel includes a plurality of gate lines arranged in a vertical direction and each extending in a horizontal direction for driving the gates of TFTs arranged in a row, and a plurality of data lines arranged in the horizontal direction and each extending in the vertical direction for supplying display data to the pixels arranged in a column direction.
The drive unit
200
includes a vertical driver
210
fro driving the gate lines and a horizontal driver
220
for driving the data lines. When the vertical driver
210
supplies a scanning signal to a horizontal gate line for turning on the corresponding TFTs in the row, and the horizontal driver supplies a display data to each of the vertical data lines, an analog display signal is supplied to the pixel electrode through a corresponding TFT, whereby an electric field is applied to the liquid crystal between the pixel electrode and the common electrode. The electric field generates a chemical change in the liquid crystal for displaying an image based on the display data.
Assuming that the LCD panel defines 1024 (horizontal)×768 (vertical) pixels therein, the configurations of the vertical driver
210
and the horizontal driver
220
are such that:
(1) the horizontal driver drives 3072 (3×1024) data lines each assigned for red, green and blue, and includes eight cascaded driving sections each having a function fro driving
384
data lines and arranged at the top of the LCD panel; and
(2) the vertical driver drives
768
gate lines and includes four cascaded driving sections each having a function for driving
192
gate lines and arranged at one side of the Lcd panel.
Each of the vertical and horizontal drivers
210
and
220
is implemented on a single IC chip, which is mounted on a TCP (tape carrier package) and disposed with the longer sides thereof being parallel to a corresponding side of the LCD panel.
The horizontal driver
220
, such as shown in
FIG. 2
, delivers display data to the data lines S
1
to S
384
including R, G and B color data having a positive or negative polarity with 64 gray-scale levels so that each data line S
1
to S
348
receives an alternate driving signal, and so that an odd-numbered data line S
1
, S
3
, S
5
, . . . and an even-numbered data line S
2
, S
4
, S
6
, . . . receive driving signals having different polarities in each horizontal period.
The horizontal driver
220
includes a shift register
221
, a data register block
222
, a latch block
223
, a level shifter block
224
, a D/A converter block
225
and an output stage block
226
including voltage followers. The shift register
221
is a 64-bit bi-directional register, which responds to a direction selection signal to select a right-shift operation or a left-shift operation for shifting a start pulse. The direction of the shift pulse is determined during the initial adjustment of the device. The shift register
221
reads a high level of a start pulse at a rising edge of a clock signal, generates successive control signals for the data register block
222
by shifting the start pulse, and delivers the control signals for controlling the data register
222
to receive input display data.
A group of six 6-bit data registers in the data register block
222
reads 6-bit display data at a time based on the control signals of the shift register
221
. Each latch in the data latch block
223
responds to a rising edge of a latch control signal to latch the display data from the data register block
222
, whereby the data latch block
222
delivers the display data for one row in a horizontal period through the level shifter block
224
to the D/A converter block
225
. The D/A converter block
225
generates 64-level gray-scale voltages having a positive polarity and 64-level gray-scale voltages having a negative polarity in a gray-scale voltage generator of D/A converter block
225
, consecutively selects one of the gray-scale voltages based on a display data by using a ROM decoder thereof, and delivers a gray-scale signal having a selected one of the gray-scale voltages through the voltage follower
226
as a driving voltage for driving each data line. The driving voltages for the data lines are such that each odd-numbered data line S
1
, S
3
, S
5
, . . . and each even-numbered data line S
2
, S
4
, S
6
, . . . are driven by the driving voltages having different polarities in each horizontal period, and each data line S
1
to S
348
receives alternately a positive-polarity signal and a negative-polarity signal in each horizontal period.
Referring to
FIG. 3
, a semiconductor chip
301
implementing the horizontal driver
220
of FIG.
2
and mounted on a TCP is exemplified. The horizontal driver
220
has a function for driving 384 data lines, for example. The semiconductor chip
301
has a rectangular shape in the top plan view thereof, and includes the horizontal driver
220
as an internal circuit
302
. The semiconductor chip
301
has output pads (not depicted) consecutively disposed on the side near the LCD panel for driving the data lines S
1
, S
2
, . . . S
384
therein, input pads disposed on the side opposing the output pads for receiving the start pulse, shift direction switching signal, clock signal, input data, and latch control signal, and power source pads arranged adjacent to the input pads for receiving power sources and &ggr;-correction sources. The output pads may be disposed at the shorter sides of the semiconductor chip
301
.
Referring to
FIG. 4
, therein shown an example of the internal circuit
302
, which is depicted to drive six data lines S
1
to S
6
out of 384 data lines as an abbreviation.
The internal circuit
302
includes a shift register
311
, one stage of which corresponds to the number (six in this case) of data lines S
1
to S
6
, a data register block
312
having registers in number (6) corresponding to the number of data lines S
1
to S
6
, a first switch block
313
having three 2-input/2-output switches each for exchanging outputs from a pair of registers in the data register block
312
, a latch block
314
having latch cells each for latching data output from the first switch block
313
, a level shifter block
315
having level shifters each for level-shifting an output from the latch block
314
, a D/A converter block
317
having three 2-input/2-output switches each for exchanging outputs from a pair of converter cells in the D/A converter block
316
, and an output stage block
318
having voltage followers for transferring an output from the second switch block
317
. These circuit elements in each circuit clock are consecutively arranged in the vicinity of the longer side of the semiconductor chip
301
near the LCD panel conforming to the arrangement of the data lines.
In operation of the internal circuit
302
, if a right-shift operation, for example, is selected in the shift register
311
, the shift register
311
reads a high level of the start pulse at a rising edge of the clock signal for each horizontal period, and delivers the start pulse toward the next stage disposed at the right hand side in the internal circuit
302
. At the same time, the control signals for receiving data are also d
Kosaka Yasuhiro
Shimizu Nobuo
Jorgensen Leland R.
McGinn & Gibb PLLC
NEC Electronics Corporation
Saras Steven
LandOfFree
Driver unit for driving an active matrix LCD device in a dot... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Driver unit for driving an active matrix LCD device in a dot..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Driver unit for driving an active matrix LCD device in a dot... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3066745