Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-12-04
2003-02-11
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C363S060000
Reexamination Certificate
active
06518829
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to a driver timing and circuit technique for a low noise charge pump circuit of particular applicability with respect to IC devices requiring voltage levels either in excess of, or lower than, externally supplied voltages.
IC devices are typically designed to require only a power (“VCC”) and a relative circuit ground (“VSS”) voltage supplies. This increases the ease of use of the IC device in a system. Nevertheless, in some cases subcircuits of these devices require voltage supply levels above or below these levels for proper operation.
Current dynamic random access memory (“DRAM”) devices frequently require a voltage supply level above VCC to drive the memory access transistor gate or row decoder logic to sufficiently high levels such that a full VCC level can be written into the memory cell. DRAMs also frequently require a voltage level below VSS which is used to bias the substrate to prevent minority carrier injection from peripheral circuits. In addition, electrically erasable programmable read-only memory devices (“EEPROMs”) frequently require a voltage supply level higher than VCC in order to program or erase memory cells.
In this regard, voltage levels higher than VCC are often generated on the IC device itself (i.e. “on-chip” by means of charge pump circuits. A charge pump circuit utilized to derive a voltage above the level of VCC generally operates by connecting a first node of a capacitor to VCC while the second node is connected to VSS; disconnecting the first node of the capacitor from VCC and connecting it to a pumped node (“VCCP”); disconnecting the second node of the capacitor from VSS and driving it to VCC thereby driving the first node above VCC and coupling the first node of the capacitor to the pumped node transferring charge to it; disconnecting the first node of the capacitor from the pumped node and reconnecting it to VCC; disconnecting the second node from VCC and connecting again to VSS thereby restoring the initial state of the capacitor and repeating the steps resulting in charge being “pumped” from VCC to VCCP.
In those applications wherein VCCP is required to provide relatively large amounts of current, the capacitor and transistors in the charge pump must also be large in size. When the transistors switch “on” and “off” to drive the capacitor nodes “high” or “low”, large amounts of current flow and the rate of change of the current (“dI/dt”) flow is also large. Because the voltage supplies VCC and VSS are sourcing and sinking this current, the VCC and VSS voltage levels vary as a result of the charge pump operation. This voltage variation constitutes undesired “noise” and this noise on the VSS and VCC supplies can cause an IC device to fail to function properly in a system. The amount of noise is determined by the resistance and inductance of the VCC and VSS supplies, and for IC devices, the most difficult source of noise to control is that due to the dI/dt factor because the die bond wires present significant levels of inductance.
In conventional charge pump circuits, the pump capacitor is driven by an inverter causing a relatively large change in current over time (“dI/dt”) to occur when the capacitor node is driven and when the transistor connecting the intermediate node to the power supply is turned “on”. A similar dI/dt also occurs when the transistor connecting the intermediate node to the pumped node is turned “on”. These dI/dt changes at the capacitor and intermediate nodes result in undesired and sometimes unacceptable noise in the circuit.
SUMMARY OF THE INVENTION
In accordance with the technique of the present invention, the pump capacitor of a driver circuit for an integrated circuit device is driven “high” by one transistor and “low” by another. By correctly sizing the devices driving them, each transistor can be turned “off” quickly and “on” slowly and, in an alternative embodiment, both transistors may be “off” at the same time resulting in “tri-state” operation. Timing may be set such that both transistors are “off” when the transistor connecting the intermediate node to the power supply is turned “on” thereby preventing a large dI/dt and resultant noise on the power supply sources.
Particularly disclosed herein is an integrated circuit device including a charge pump circuit which comprises a capacitive element having first and second terminals coupled to an intermediate and capacitor
62
nodes respectively. A first switching device is
52
provided for selectively coupling the intermediate node to a supply voltage line in response to a first clocking signal together with a second switching
54
device for selectively coupling the intermediate node to a pumped voltage line in response to a second clocking signal. A first inverter
66
has an input coupled to receive a third clocking signal and an output coupled to a third switching device
58
for selectively coupling the capacitor node to the supply voltage line in response to the third clocking signal; and a second inverter
72
has an input coupled to also receive the third clocking signal and an output coupled to a fourth switching device
60
for selectively coupling the capacitor node to a ground voltage line in response to the same third clocking signal. In an alternative “tri-state” embodiment, the second inverter has its input coupled to receive a separate fourth clocking signal and is operative to cause the fourth switching device to couple the capacitor node to the ground voltage line in response thereto independently of the third clocking signal.
Also particularly disclosed herein is a method for operating a charge pump in an integrated circuit device which comprises the steps of coupling a first terminal of a capacitive element to a supply voltage line while a second terminal of the capacitive element is coupled to a ground voltage line. The first terminal is firstly decoupled from the supply voltage line while substantially concurrently coupling the first terminal to a pumped voltage line. The second terminal is secondly decoupled from the ground voltage line while substantially concurrently coupling the second terminal to the supply voltage line. The first terminal is thirdly decoupled from the pumped voltage line while substantially concurrently coupling the first terminal to the supply voltage line. The second terminal is then fourthly decoupled from the supply voltage line while substantially concurrently coupling the second terminal to the ground voltage line. In operation, the step of secondly decoupling the second terminal from the ground voltage line occurs relatively more quickly than the corresponding step of substantially concurrently coupling the second terminal to the supply voltage line. Also, the step of fourthly decoupling the second terminal from the supply voltage line may also occur relatively more quickly than the corresponding step of substantially concurrently coupling the second terminal to the ground voltage line.
REFERENCES:
patent: 5703511 (1997-12-01), Okamoto
patent: 5801578 (1998-09-01), Bereza
patent: 6008690 (1999-12-01), Takeshima et al.
patent: 6018264 (2000-01-01), Jin
patent: 6097161 (2000-08-01), Takano et al.
patent: 6107862 (2000-08-01), Mukainakano et al.
patent: 6147519 (2000-11-01), Krynski
patent: 6198340 (2001-03-01), Ting et al.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
United Memories Inc.
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