Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-12-07
2001-10-16
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S209000, C345S079000, C345S098000, C345S100000
Reexamination Certificate
active
06304241
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to liquid crystal display panels and, more particularly to a driver for a liquid-crystal display panel, the driver having a reduced circuit area and power consumption and improving the picture quality of the liquid-crystal display panel.
To prolong the life of the liquid-crystal display panel, the driver has reversed the polarity of the picture voltage supplied to each pixel (picture element) cell of the liquid-crystal display panel (LCD panel).
FIG. 1
is a partial block circuit diagram of a data driver
11
for a conventional liquid-crystal display panel. The data driver
11
comprises a plurality of pairs of first and second digital-to-analog (D/A) converters
12
and
13
, plural sets of output terminals P
1
, P
2
, P
3
, and P
4
, a plurality of pairs of polarity changeover switches
16
and
17
, shift registers and latch circuits (neither are illustrated). The latch circuits latch digital picture signals supplied from external devices in accordance with latch control pulse signals from the shift registers.
A pair of the polarity changeover switches
16
and
17
are connected between the first and second D/A converters
12
and
13
and a pair of the output terminals, respectively. The changeover switch
16
selectively connects the output terminal of the first or second D/A converter
12
or
13
and the odd-numbered output terminal P
1
(P
3
). The changeover switch
17
selectively connects the output terminal of the first or second D/A converter
12
or
13
and the even-numbered output terminal P
2
(P
4
). Each of the polarity changeover switches
16
and
17
comprises first and second switches
18
and
19
.
Each of the first and second D/A converters
12
and
13
comprises a selector
14
and an op amp
15
. The selector
14
of the first D/A converter
12
receives the picture signal from the latch circuits as a first picture signal Vd
1
(Vd
3
) and receives first gradation voltages Va
1
to Va
64
. The selector
14
selects one of the first gradation voltages Va
1
to Va
64
in accordance with the first picture signal Vd
1
(Vd
3
) and outputs the selection signal to the op amp
15
. The op amp
15
outputs the selected voltage as a segment voltage. Thus, the first D/A converter
12
receives the first picture signal Vd
1
(Vd
3
) and the first gradation voltages Va
1
to Va
64
and outputs a segment voltage (positive-polarity voltage) which is higher than a common voltage.
The selector
14
of the second D/A converter
13
receives the picture signal from the latch circuits as a second picture signal Vd
2
(Vd
4
) and receives second gradation voltages Vb
1
to Vb
64
. The selector
14
selects one of the second gradation voltages Vb
1
to Vb
64
in accordance with the second picture signal Vd
2
(Vd
4
) and outputs the selected voltage to the op amp
15
. The op amp
15
outputs the selected voltage as a segment voltage. Thus, the second D/A converter
13
receives the second picture signal Vd
2
(Vd
4
) and the second gradation voltages Vb
1
to Vb
64
and outputs a segment voltage (negative-polarity voltage) which is lower than the common voltage.
The first switch
18
of the polarity changeover switch
16
is connected between the output terminal of the first D/A converter
12
and the odd-numbered output terminal P
1
(P
3
). The first switch
18
of the polarity changeover switch
17
is connected between the output terminal of the second D/A converter
13
and the even-numbered output terminal P
2
(P
4
).
The second switch
19
of the polarity changeover switch
16
is connected between the output terminal of the first D/A converter
12
and the even-numbered output terminal P
2
or P
4
. The second switch
19
of the polarity change over switch
17
is connected between the output terminal of the second D/A converter
13
and the odd-numbered output terminal P
1
or P
3
.
The first and second switches
18
and
19
complementarily turn on and off every one horizontal scanning period in response to a polarity switching signal FR. Accordingly, the positive-polarity segment voltage and the negative-polarity segment voltage are alternately supplied to each of the output terminals P
1
to P
4
every one horizontal scanning period.
For example, in response to the polarity switching signal FR, when the first switch
18
turns on and the second switch
19
turns off, the positive-polarity segment voltage from the first D/A converter
12
is applied to the odd-numbered output terminal P
1
(P
3
) and the negative-polarity segment voltage from the second D/A converter
13
is applied to the even-numbered output terminal P
2
(P
4
).
During the next horizontal period, when the first switch
18
turns off and the second switch
19
turns on, the positive-polarity segment voltage from the first D/A converter
12
is applied to the even-numbered output terminal P
2
(P
4
) and the negative-polarity segment voltage from the second D/A converter
13
is applied to the odd-numbered output terminal P
1
(P
3
).
The segment voltage applied to each output terminal is supplied to the pixel cell of the liquid-crystal display panel through a data line. The display level (brightness) of the pixel cell changes depending on the potential difference between the common voltage and a segment voltage Vs. Because the pixel cell comprises a liquid crystal cell and an auxiliary storage capacitor, the liquid-crystal display panel has a capacitive load on the data driver. Hence, the first D/A converter
12
charges the pixel cell through the data line and the second D/A converter
13
discharges a stored electric charge from the pixel cell through the data line. This charge/discharge operation increases the power consumption of the liquid crystal display panel as the number of horizontal pixel cells increases.
FIG. 2
is a partial block diagram of an improved data driver
21
for preventing the increase of power consumption. The data driver
21
comprises D/A converters
22
that correspond to the number of output terminals. Each of the D/A converters
22
comprises a selector
23
and an op amp
24
, receives a picture signal Vd and gradation voltages V
1
to V
128
, and alternately outputs the positive-polarity segment voltage Vs
1
and the negative-polarity segment voltage Vs
2
. The gradation voltages V
65
to V
128
are positive-polarity segment voltages higher than the common voltage applied to each of the pixel cells, and the gradation voltages V
1
to V
64
are positive-polarity segment voltages lower than the common voltage. Accordingly, each of the D/A converters
13
alternately outputs one of the gradation voltages V
65
to V
128
and one of the graduation voltages V
1
and V
64
as the segment voltage Vs. During the same horizontal scanning period, the polarities of the gradation voltages selected by adjacent D/A converters
13
differ each other.
For example, as shown in
FIG. 3
a
, the first D/A converter
22
alternately outputs a positive-polarity segment voltage Vsa and a negative-polarity segment voltage Vsb every one horizontal scanning period. The second D/A converter
23
, adjacent to the first D/A converter
22
, as shown in
FIG. 3
b
, alternately outputs the negative-polarity segment voltage Vsb and the positive-polarity segment voltage Vsa every one horizontal scanning period.
Switches
25
are connected between the adjacent odd-numbered output terminal P
1
(P
3
) and the even-numbered output terminal P
2
(P
4
). Each of the switches
25
turns on for a predetermined period (for example, a retrace period which is a nonselective period of the pixel cell) in response to a control signal ER, and an electric charge moves from the data line charged to the positive-polarity voltage to the data line discharged to the negative-polarity voltage through the switches
25
. In this case, the D/A converters
22
are maintained in the high impedance state. This charge/discharge allows the voltages of the data lines connected to the output terminals P
1
to P
4
to move to the vicinity of the common v
Kokubun Masatoshi
Udo Shinya
Yamagata Seiji
Fujitsu Limited
Greer Burns & Crain Ltd.
Hjerpe Richard
Nguyen Frances
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