Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-10-30
2010-11-09
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169400
Reexamination Certificate
active
07830336
ABSTRACT:
An output buffer circuit constituted by a totem-pole circuit where two NchMOS transistors are cascade-connected, and the connection point of the two MOS transistors are connected to a data electrode of a display cell, improves the power recovery rate of a driver device of a PDP. A level shift circuit includes a CMOS circuit and drives the output buffer circuit. An electric charge recovery circuit connected to a power supply of the output buffer circuit recovers and reuses electric charges remaining on the data electrode after the discharge of the display cells. A power supply control circuit controls so that the power supply voltage of the level shift circuit is higher than the sum of the power supply voltage of the output buffer circuit and the threshold voltage of the MOS transistors for a period of time during a recovery/reuse cycle of the electric charge recovery circuit.
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Bedell Daniel
McGinn IP Law Group PLLC
NEC Electronics Corporation
Shalwala Bipin
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