Driver circuit with reduced jitter between circuit domains

Details Driver circuit with reduced jitter between circuit domains Driver circuit with reduced jitter between circuit domains

2005-10-27

2008-08-12

Richards, N. Drew (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S062000

Reexamination Certificate

active

07411439

ABSTRACT:
A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized. Thus, a transition from an internal supply potential to an external supply potential may take place, without noticeably degrading the signal timing.

REFERENCES:
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 5149990 (1992-09-01), Yamazaki et al.
patent: 5926050 (1999-07-01), Proebsting
patent: 5990706 (1999-11-01), Matsumoto et al.
patent: 6025738 (2000-02-01), Masleid
patent: 6154045 (2000-11-01), Ye et al.
patent: 6424173 (2002-07-01), Vannorsdel
patent: 6515532 (2003-02-01), Jinzai
patent: 6630851 (2003-10-01), Masleid
patent: 6784719 (2004-08-01), Okamoto et al.
patent: 7190206 (2007-03-01), Lee et al.
patent: 7251740 (2007-07-01), Newman
patent: 7292217 (2007-11-01), Tseng et al.
patent: 2001/0017783 (2001-08-01), Bruckmann et al.
patent: 2002/0039042 (2002-04-01), Jinzai
patent: 2003/0137336 (2003-07-01), Okamoto et al.
patent: 2005/0017783 (2005-01-01), Lee et al.
patent: 10 2004 036 892 (2005-02-01), None
patent: 1 326 342 (2003-07-01), None
Lee, J.B., et al., “Digitally-Controlled DLL and I/O Circuits for 500 Mb/s/pin x16 DDR SDRAM,”ISSCC 2001/Session 4/High-Speed Digital Interfaces/4.6, 2001 IEEE International Solid State Circuits Conference, 3 pages.
Kanno, Y., et al., “Level Converters with High Immunity to Power-Supply Bouncing for High-Speed Sub-1-V LSIs,” 2000 IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 202-203.

Affiliated with

Also associated with

Rating

Driver circuit with reduced jitter between circuit domains does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Driver circuit with reduced jitter between circuit domains, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Driver circuit with reduced jitter between circuit domains will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4002617