Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-04-18
2003-04-01
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S206000
Reexamination Certificate
active
06542011
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit and a receiver circuit that can be applied to the transfer of digital information such as data in a semiconductor integrated circuit, and a technique for the transfer of digital signals.
2. Background
Signals handled in a semiconductor integrated circuit device are digital signals of pulse waveforms, and the transfer of signals is performed through metal wiring or the like formed in the same substrate. Since metal wiring is generally formed having a small cross-sectional area, wiring resistance is large, and coupling capacitance between wirings is large. Increase in wiring resistance and wiring capacitance increases the time constant of the pulse response, and causes pulse waveforms transferred through the wiring to become blunt. The blunt pulse may cause the clock of the signal transfer to become delayed, or the reliability of the signal transfer to decrease. Therefore, a driver circuit and a receiver circuit are used for ensuring the transfer of signals from the transmission side to the reception side. Since the signals received by the receiver circuit are of a blunt pulse form, and noise from adjacent metal wiring or the like is overlapped during the transfer of the signals, the pulse waveform is corrected by the receiver circuit. For the transfer of digital signals, the following methods are used.
FIG. 14
is a circuit diagram showing an example of conventional circuits for the transfer of digital signals. Two stages of inverters
101
and
102
configure the driver circuit
100
in the transmission side, which supplies input signals to the input terminal
103
of an inverter
101
of a first stage. The output of the second inverter
102
is from the output terminal
104
of the driver circuit, and signals that have been fully swung between the power supply voltage (e.g. 2.5 V) and the reference voltage (e.g. ground potential: 0 V) are outputted. The outputted signals are transferred through the signal line
105
, and supplied to the input terminal
107
of the receiver circuit
106
. The receiver circuit
106
is configured by a NOT circuit (inverter)
108
and a NAND circuit
109
. The waveform of the input signal is corrected by the NOT circuit
108
, and inputted to the NAND circuit
109
. An action signal (ACT), i.e. a clock signal, is inputted to another input terminal of the NAND circuit
109
. The output of the NAND circuit
109
is outputted from the output terminal
110
as the output of the receiver circuit
106
.
FIG. 15
is a graph showing the simulated voltage waveforms at main parts of the circuit of FIG.
14
. The waveform of the signal inputted to the input terminal
103
is shown by FIG.
15
(
a
). The waveform of the signal after transferred through the signal line
105
and before inputted to the NOT circuit
108
is shown by FIG.
15
(
b
). Bluntness is seen in this waveform. The output waveform of the NOT circuit
108
is shown by FIG.
15
(
c
), and the blunt input waveform FIG.
15
(
b
) has been corrected. The ACT signal is shown by FIG.
15
(
d
), and the voltage waveform of the output terminal
110
is shown by FIG.
15
(
e
). The ACT signal acts as the clock. The simulation conditions are: a line length of 9 mm for the signal line
105
, a wiring load capacitance of 2.1 pF (of which load capacitance connected to the signal line is assumed as 500 fF), and a wiring resistance of 360 ohms.
FIG. 16
is a circuit diagram showing another example of a conventional digital signal transfer circuit. The driver circuit
120
is an n-type MISFET (n-type Metal Insulator Semiconductor Field Effect Transistor: hereafter an n-type MISFET is called NFET)
122
that discharges the electric charge pre-charged in the signal line
121
, and the input signal is supplied to the input terminal
123
, which is the gate of the NFET
122
. The receiver circuit
124
is provided with an NFET
125
, the gate of which is supplied with a reference voltage Vref, and a p-type MISFET (hereafter a p-type MISFET is called PFET)
126
for pre-charging is connected to the drain side of the NFET
125
. An action signal ACT is supplied to the gate of the PFET
126
, and when ACT is at Low level, the PFET
126
is turned ON, and the sense line
128
(the drain side of the NFET
125
) is connected to the power supply voltage Vdd (e.g. 2.5V). At this time, the source side of the NFET
125
(signal line
121
) is charged until the value becomes Vref minus the threshold voltage. The PFET
127
is an FET that has pull-up action for enhancing noise resistance when the sense line
128
is at High level while the ACT is at High level. The size of the PFET
127
is much smaller than the PFET
126
.
FIG. 17
is a graph showing simulated operational waveforms of the circuit of FIG.
16
. The input signal voltage at the input terminal
123
is shown by FIG.
17
(
a
), the ACT signal is shown by FIG.
17
(
b
), and the output signal voltage at the output terminal
130
is shown by FIG.
17
(
c
). The line (d) shows the change in the voltage of the sense line
128
, and the line (e) shows the change in the voltage of the signal line
121
. Under the conditions where the ACT is at Low level, and the signal line
121
is pre-charged (t<t
1
in FIG.
17
), the ACT is switched to High level (t=t
1
) to make the receiver circuit
124
read enabled. At this time, an input signal is inputted to the input terminal
123
. When a High level is inputted (FIG.
17
(
a
)), the NFET
122
is turned ON, and the voltage of the signal line
121
is lowered (line (e) in FIG.
17
). The lowered voltage is transferred to the source of the NFET
125
, and when the source potential is lowered to or below the voltage determined by Vref and the threshold voltage, the NFET
125
is turned ON, and the charge of the sense line
128
is rapidly transferred to the source side. And when the sense line
128
becomes Low level, a High level is outputted from the output terminal
130
connected through the inverter
129
. At this time, since the PFET
127
is always ON, an ON current flows through the PFET
127
; however, since the size of the PFET
127
is small, and the ON current is extracted by the NFET
122
as long as the NFET
122
is ON, the sense line
128
is kept at Low level.
In the method as described above, the digital signal is transferred from the driver circuit to the receiver circuit through the signal line.
However, with the increase in the density and performance of semiconductor integrated circuits in recent years, the number of devices integrated in a single semiconductor substrate (chip), and the length of wiring (signal lines) formed in the chip tend to increase. In the case of a DRAM (dynamic random access memory) for example, the length of wiring such as an address signal line becomes several. millimeters to several-tens of millimeters long, whereby parasitic capacitance (floating capacitance) and wiring resistance accompanying a signal line increase. Parasitic capacitance and wiring resistance accompanying wiring cause the form of pulses that pass through the wiring to be deformed, thereby causing the delay of signal transmission. Also, the parasitic capacitance and wiring resistance increases the power consumption due to wiring.
When a conventional transmission circuit as shown in
FIG. 14
is used, the output
104
of the driver circuit
100
is driven by the source voltage of 2.5 V and the reference voltage of 0 V, and the amplitude can be as large as 2.5 V. Therefore, charge-discharge current increases due to wiring capacitance in the address signal line or the like with long wiring. For example, the result of the simulation of the average current consumption waveform obtained under the above-described simulation conditions, assuming that the input signal is 125 MHz and the operating frequency of the receiver circuit
106
is 250 MHz, is about 1 mA as
FIG. 18
shows. If the total of address, bank, and command lines is assumed as
20
, these consume 20 mA. Current consumption must be redu
Canale Anthony J.
International Business Machines - Corporation
Walsh Robert A.
Wells Kenneth B.
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