Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1998-09-14
2001-01-09
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S023000, C327S027000
Reexamination Certificate
active
06172541
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to communication circuits, and is particularly directed to a driver circuit that may be used for driving a load, such as a digital communication line, in accordance with data transitions in an input signal, so that the amplified output signal driving the line conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics (e.g., capacitance) of the line being driven.
BACKGROUND OF THE INVENTION
Suppliers of digital communication circuits, such as those employed for transmitting digital data, including, but not limited to an RS-232 formatted digital data stream, must conform with user specifications that define maximum and minimum limits on slew rate, as well a rise and fall time boundaries of signal transitions in the transmitted data. Unfortunately, the characteristics (especially capacitance) of the loads (lines) to which such digital data transmission equipment may be connected can be expected to vary from line to line, so that the performance of the equipment is potentially susceptible to the unknown variations in the properties of the line.
The conventional practice to handle these variations has been to drive the line hard by means of a high gain operational amplifier and hope that the capacitance of the line (which typically may fall anywhere between 50 and 2500 picofarads) will not significantly distort the output signal (take the circuit's performance outside of spec.). The fundamental problem with this approach is the fact that the load, which may be typically represented as a parallel RC circuit coupled between the amplifier's output node and ground, effectively becomes part of the circuit and thereby affects the time constant properties (slew rate and rise/fall times) of the amplified driving signal.
SUMMARY OF THE INVENTION
In accordance with the present invention, the shortcomings of such a conventional digital line driver are effectively obviated by a predefinable slew rate driver circuit which employs load-monitoring feedback to maintain the slew rate of the driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of variable characteristics (such as capacitance) of the line.
Two embodiments of the invention are described. In a first, slew rate control is effected by adjusting (increasing or decreasing) the amount of charge on a storage device (such as a capacitor, variable threshold MOSFET, and the like, as non-limiting examples), and thereby the drive current to an output driver circuit, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to the termination of a prescribed time window. In a second embodiment, slew rate control is effected by directly determining the length of time required for the output terminal to transition between first and second states thereof, and adjusting the operation of the output driver, in accordance with whether the total time measurement is greater than or less a prescribed slew rate window.
In the first embodiment of the invention, a controlled load/line driver device, such as a field effect transistor (FET), has its drain-source path coupled in circuit between an output terminal to which a (capacitive) load is coupled and a line driving supply rail. The drive control signal applied to the gate of the driver FET is supplied by way of a drive signal control FET. The drive signal control FET has its source-drain path coupled in circuit with an inverter, complementary FETs of which have their gates coupled to an input terminal, to which the driver switching signal is applied.
To reduce the power dissipation and control the shape of the load-driving output signal produced in the linear region of operation of the driver FET, a threshold-based gate drive control circuit is coupled in circuit with the gate of the output driver FET and the output terminal. This threshold based gate drive control circuit is operative to compare the gate voltage applied to the gate of the driver FET with its drain voltage applied to the output terminal. If the monitored gate-to-drain differential of the driver FET drops below a prescribed value (e.g., 0 volts), the drive control circuit rapidly pulls the gate of the driver FET to GND.
A charge storage device, such as a capacitor, is coupled to the gate of the drive signal control FET and is operative to store a charge that is used to establish the drive current for drive signal control FET, and thereby the magnitude of the drive control signal applied to the gate of the load-driving drive FET. The charge stored by the storage device (e.g., capacitor) is controllably adjustable by means of controlled charging and discharging circuit, the operation of which is controlled in accordance with the switching control signal applied to the input terminal and an error signal from an output terminal-monitoring circuit.
The controlled charging and discharging circuit is operative to adjustably increase or decrease the amount of stored charge, so that the rate at which the voltage at the output terminal switches between first and second states thereof satisfies a prescribed slew rate, as determined by the timing window of a monostable one-shot circuit, to which the input terminal is coupled. The controlled charging and discharging circuit may comprise a pair of complementary FETs, having their respective source-drain paths coupled in circuit between first and second voltage supply rails. A common connection of the drains of the FETs is coupled to the charge storage device, while their gates are coupled to logic circuitry which monitors the output terminal-monitoring circuit, the output a timing window monostable one-shot circuit and the switching control signal. The output terminal-monitoring circuit comprises a voltage threshold comparator having a first input coupled to a prescribed (Zener) voltage reference, a second input coupled to the output terminal, and an output terminal coupled to the controlled charging and discharging circuit.
In operation, in response to a switching control signal transition at the driver circuit's input terminal, the gate of the driver FET becomes coupled to the drain of the drive signal control FET, whose drain current is dependent upon the charge currently stored on the charge storage device. Since the rate of change of the drain voltage of the output driver FET (which is applied to the load) is dependent upon the capacitance of the load and the voltage on the gate of the driver FET, the larger the capacitance of the load, then the longer will be the charging/switching time and the larger the charge stored by the charge storage device. Conversely, for a smaller load capacitance, the shorter its charging/switching time and the lower the charge stored by the storage device.
In order to monitor the slew rate of the voltage at the output terminal, the time at which the voltage at the output terminal reaches a prescribed threshold is compared with the timing window of the one-shot. If the time at which the voltage at the output terminal reaches this threshold is within the timing window of the one-shot (i.e., sooner than the expiration of the timing window), then it is inferred that the drive current to the driver FET is too large, so that the charge by the charge storage device is reduced. On the other hand, if the time at which the voltage at the output terminal reaches the prescribed threshold is beyond the termination of the timing window of the one-shot (i.e., later than the expiration of the timing window), it is inferred that the drive current to the driver FET is too small and the charge by the storage device is increased.
In the second embodiment of the invention, slew rate control is made by directly determining the l
Pullen Stuart W.
Young William R.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Callahan Timothy P.
Intersil Corporation
Nguyen Hai L.
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