Driver circuit for use in an output buffer

Details Driver circuit for use in an output buffer Driver circuit for use in an output buffer

1979-05-21

1981-09-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307481, 307578, H03K 5135, H03K 1710, H03K 17284, H03K 19096

Patent

active

042912423

ABSTRACT:
A high speed, low power clocked driver circuit is provided. DC paths from voltage V.sub.DD to ground is eliminated by carefully clocking field effect transistors within the driver circuit. By using bootstrapping techniques, the output of the circuit approaches V.sub.DD. Two of the high speed, low power driver circuits are combined to drive a ratioless output circuit in order to provide an output buffer circuit having a TTL compatible output.

REFERENCES:
patent: 3575613 (1971-04-01), Ebertin
patent: 3835457 (1974-09-01), Yu
patent: 3868657 (1975-02-01), Hoffman et al.
patent: 3906464 (1975-09-01), Lattin
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4122361 (1978-10-01), Clemen et al.
patent: 4239991 (1980-12-01), Hong et al.
Arzubi, "In-Phase Driver Circuit"; IBM Tech. Discl. Bull.; vol. 19, No. 1, pp. 31-32; 6/1976.
Cox et al., "An Fet 4-Phase Dynamic Off-Chip Driver with Polarity Hold"; IBM Tech. Discl. Bull.; vol. 17, No. 2, pp. 466-467; 7/1974.

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