Driver circuit for high-voltage power transistors providing prot

Details Driver circuit for high-voltage power transistors providing prot Driver circuit for high-voltage power transistors providing prot

1986-06-20

1987-12-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307254, 307255, 307311, H03K 1760, H03K 326, H03K 1924

Patent

active

047163046

ABSTRACT:
For driving each power transistor of a three phase bridge rectifier for utilizing d.c. electric power for the control and energization of a motor, each individual power transistor is provided with an individual driver circuit supplied an individual power supply. Each power transistor in such a rectifier has a reverse voltage free wheeling diode connected between emitter and collector. Each individual driver circuit has its input control signal supplied through a galvanic isolation stage in the form of an optical coupler and the power supply has its input connection to a source of power galvanically isolated by a transformer, supplying a relatively high frequency for powering the rectifier of the driver power supply. The final driver stage utilizes Darlington transistor combinations of complementary types, one Darlington combination being supplied with negative voltage and the other being supplied with positive voltage, by the power supply rectifier. The intermediate neutral voltage of the rectifier is connected galvanically to the emitter of a power transistor and the output connection coming from the junction of the two Darlington combinations is connected to the base electrode of the power transistor. The collector of the power transistor is connected to the control logic state that controls the driver input, this connection being made through a diode (60) for preventing the power transistor from being turned on while the reverse relief diode of the power transistor is conducting. The control logic circuit has a first bistable circuit (35) for setting the on periods of the driver and power transistor and a second bistable circuit (51,53) for registering an error condition and responding thereto by preventing the setting of the first bistable circuit.

REFERENCES:
patent: 4075511 (1978-02-01), Lewis
patent: 4345164 (1982-08-01), Gies

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