Driver circuit for high speed data

Details Driver circuit for high speed data Driver circuit for high speed data

1998-03-04

2001-02-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S108000, C327S374000, C326S027000, C326S058000, C326S086000

Reexamination Certificate

active

06194949

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to digital data transmission and, more particularly, to a high-speed driver circuit for digital data transmission.
BACKGROUND OF THE INVENTION
Data transmission of high-speed data at rates having bit periods on the order of one nanosecond over distances on the order of one meter requires relatively high performance interfaces, yet also requires or benefits from limited and controlled rise and fall times to minimize distortion, signal reflections, and electromagnetic interference (EMI). The root causes of distortion and reflection include skin effects in conductors, the high-frequency loss behavior of circuit board dielectric materials, and various physical discontinuities at bends, vias, and connectors. Several high speed interface standards have seen little use and success because the short rise and fall times used to limit delays and signal degradation under slow conditions (such as worst-case devices, low voltage, and high temperature) also produce excessive slew rate which leads to signal reflections and EMI, under conditions which give faster device operation. Providing the needed tight control of rise time usually introduces drive circuitry complications and requires ultimate speed capability much greater than the controlled rate. Such added complexity usually significantly increases signal propagation time through such driver circuitry. When factors such as supply voltage, temperature, and device manufacturing tolerances are taken into account, it is common for circuits to have a two-to-one practical range or even wider ranges in speed performance. Such wide ranges require either system designs predicted on the lowest-performance circuits or selection of the higher-performance circuits, with consequent waste of the lower-performance circuits.
PROBLEMS SOLVED BY THE INVENTION
The present invention achieves the required regulation of output rise and fall times in a data line driver with no increase in signal propagation delay other than that of the rise and fall times themselves and with no increase in complexity or power dissipation over drivers of the prior art.
PURPOSE, OBJECTS, AND ADVANTAGES OF THE INVENTION
The purpose of the invention is providing an improved high-speed driver circuit for digital data transmission, having much reduced variation in rise and fall times. Thus one object of the invention is reduction of variation in data rise and fall times in comparison with driver circuits available heretofore. Another object is avoiding significant increases in complexity and signal propagation time. A related object is a driver circuit using a minimum number of devices. Another object is providing such driver circuits at low cost and with low power consumption. A related object is providing such driver circuits made using complementary metal-oxide-semiconductor (CMOS) process technology. Other objects include minimizing susceptibility of the driver circuit to noise and to external radiation interference. Thus, a related object is a driver configuration that is fully differential. A further related object is higher characteristic line impedance as provided by differential wiring, thus allowing reduced drive current in comparison with drive currents employed in the background art. A still further related object is substantial mutual cancellation of two matched opposing signals of a differential pair, with respect to coupling to and from other signals, and with respect to coupling to and from the power supply rails. Finally, a major object is a particular new interconnection structure of input buffers and output switches in a current-limited complementary differential CMOS driver, as described herein. These and other purposes, objects, and advantages will become apparent from a reading of the following description, along with the accompanying drawings.
SUMMARY OF THE INVENTION
The driver circuit for high speed data has a complementary differential switch formed by four transistors, a bias cell containing current mirrors controlled by a reference current, two drive-current limiting devices for limiting the drive current to a required value via the bias cell, current-shunting switches, and a suitable number of buffers (logical product buffer gates), which drive each of the gate nodes of the switches. Transistors used in these buffers are limited in size to control the rate at which they operate the switches and to control the rate at which current is steered from one side of the differential switch to the other. One supply side of each of these buffers is connected to one of the current-limited supply nodes of the main output switches, thus greatly reducing variations in switching rate.


REFERENCES:
patent: 4752703 (1988-06-01), Lin
patent: 5389840 (1995-02-01), Dow
patent: 5450026 (1995-09-01), Morano
patent: 5703532 (1997-12-01), Shin et al.
patent: 5767699 (1998-06-01), Bosnyak et al.
patent: 5859566 (1999-01-01), Voorman et al.
patent: 5880599 (1999-03-01), Bruno

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