Driver circuit for driving a half bridge

Details Driver circuit for driving a half bridge Driver circuit for driving a half bridge

2000-04-20

2001-02-06

Berhane, Adolf Deneke (Department: 2838)

Electric power conversion systems

Current conversion

Using semiconductor-type converter

Reexamination Certificate

active

06185118

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a driver circuit for driving a half bridge formed by a high-side semiconductor switch and a low-side semiconductor switch that are connected in series between a first terminal and a second terminal for a supply potential, with a driver allocated to each semiconductor circuit, the drive switching the respective semiconductor switches to be either transmissive or inhibited by a drive signal, and wherein a load can be connected between the high-side and the low-side semiconductor switch.
2. Description of the Prior Art
Semiconductor switches that are interconnected with a conductor path between a first supply potential terminal, that customarily carries the positive operating voltage, and a load output are characterized as high-side semiconductor switches. Low-side semiconductor switches, on the other hand, are interconnected with a conductor path between the load output and a second supply potential terminal. The second supply potential terminal then as a rule is a reference potential, e.g. ground potential. Each of the two semiconductor switches requires a drive that switches the respective semiconductor circuit transmissive or inhibited. When connecting a semiconductor circuit to form a half bridge, only one of the two semiconductor switches may be transmissive or inhibited at a given time. The drives respectively allocated to the high-side and the low-side semiconductor switches are consequently coupled together as a rule in order to accommodate this requirement. MOSFETs can be used, for example, as the semiconductor switches.
A drive for a high-side semiconductor switch is shown in
FIG. 1
, on the basis of which the basic manner of functioning will be explained. A MOSFET T
1
is interconnected between a first supply potential terminal
1
, carrying a positive operating load V
bb
, and a load output
10
. The drain terminal of the MOSFET T
1
is connected with the first supply potential terminal
1
while the MOSFET is connected on the source side with the load output
10
. A load RL that is connected on one side with the load output
10
and on the other side with a second supply potential terminal
2
is connected in a series with the load path of the MOSFET T
1
. A reference potential, e.g. the ground potential is at the supply potential terminal
2
. Furthermore, a charge pump LP is provided that is connected to the gate of the MOSFET T
1
via a resistor R
1
.
A bipolar transistor M
3
is connected with its collector to the first supply potential terminal
1
and with its emitter to the junction between the charge pump LP and the resistor R
1
. When a voltage signal is supplied to its base by a control input ASL
1
, then the bipolar transistor M
3
becomes transmissive and it can charge the gate of the MOSFET T
1
together with the charge pump LP so that the MOSFET T
1
is transmissive.
In order to reliably inhibit the MOSFET T
1
, another MOSFET M
1
is provided that is of the opposite conductivity type as the MOSFET T
1
. The MOSFET M
1
is connected with its drain terminal via the resistor R
1
to the gate of the MOSFET T
1
, while the source terminal of the MOSFET M
1
is connected to the source terminal of the MOSFET T
1
. A drive signal complementary to the control input ASL
1
is at a control input ASS
1
that is interconnected with the gate of the MOSFET M
1
.
To inhibit the MOSFET T
1
, it is consequently necessary to inhibit the bipolar transistor M
3
with an appropriate drive signal while the MOSFET M
1
is switched transmissive by the control input ASS
1
. As a result hereof, the gate of the MOSFET T
1
is brought approximately up to the potential of the source terminal of the MOSFET T
1
, so that inhibiting the MOSFET M
1
is achieved. A detailed exemplary embodiment of a drive for a MOSFET with a source-side load is described, for example, in European Application 0 572 706.
The drive for a low-side semiconductor switch is constructed identically in principle. One can, however, omit the charge pump LP since no voltage is needed at the gate of the corresponding power switch that exceeds the operating voltage V
bb
.
Frequently, several half bridges are connected together in practice. An H-bridge circuit formed by two half bridges is known and is shown, for example, in FIG.
2
. Such a full bridge is used, e.g. for the drive of motor loads. The H-bridge circuit allows a change in direction of the load current.
The series-circuit formed by the high-side semiconductor switch T
1
and T
2
as well as the low-side semiconductor switches T
3
and T
4
is connected between the first supply potential terminal
1
and the second supply potential terminal
2
. A load RL that can be, e.g. a motor, is connected between the load outputs
10
and
10
′. The semiconductor switches T
1
and T
4
are inhibited in the present embodiment via the drives (not shown). The load current consequently flows from the first supply potential terminal
1
′ via the high-side semiconductor switch T
2
, the load output
10
′, the load RL, the load output
10
as well as the low-side semiconductor switch T
3
. In the specific exemplary embodiment of the
FIG. 2
, the low-side semiconductor switch T
3
is driven by a high frequency pulse width modulation signal while the high-side semiconductor switch T
2
is switched to permanently transmissive. As a result, regulation of the load current is possible. Dependent on the on- and off-switching of the low-side semiconductor switch T
3
, the potential of the load output
10
changes with higher frequency between the supply voltage V
bb
and the ground potential.
Dependent on the technological construction of a MOSFET, a capacitive coupling exists between the gate and the drain, or between the gate and the source. The capacitance which exist between the gate and the drain is characterized as a “Miller capacitance” (Also known as the Miller-effect capacitance). The Miller capacitance of the semiconductor circuit T
1
is indicated as C
1
dashed-lines connections.
The Miller capacitance C
1
between the gate and the drain of the high-side semiconductor switch prevents, however, the gate voltage from following the source voltage at the load output
10
in a manner corresponding to the rapid potential change produced by the pulse width modulation of the low-side semiconductor switch T
3
. If, for example, the low-side semiconductor switch T
3
is transmissive, the potential changes at the load output
10
from the operating voltage V
bb
to the ground potential. Dependent on the Miller capacitance C
1
, a gate-source-voltage forms at the high-side switch T
1
, which can briefly engage the semiconductor circuit T
1
and thereby produce an undesired quadrature-axis component. This quadrature-axis component leads to a temperature boost in the semiconductor switch T
1
and can cause undesired function disturbances to occur in the entire circuit arrangement.
Frequently, three half bridges are interconnected to a three-phase bridge arrangement that can then drive, for example, a brushless three phase motor. Since the semiconductor switches of a three-phase motor can also be driven very high-frequency by a pulse width control, disruptive quadrature-axis components are problematic here as well.
A driver circuit for driving a half bridge is disclosed, for example, in German OS 40 32 014. In the circuit arrangement described therein, the state (semiconductor switch transmissive or inhibited) of the two semiconductor switches is detected and it is assured by an appropriate drive that one of the two semiconductor switches can only be switched transmissive if the other is already in the inhibited state. To this end, down times are provided between the switching events of the individual semiconductor switches. The procedure described therein exhibits the disadvantage, however, that the semiconductor switches can not be driven at arbitrarily high frequencies. Furthermore, the problematic issue of the Miller capacitance is not taken into consideration. In the d

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