Electric power conversion systems – Current conversion – Using semiconductor-type converter
Reexamination Certificate
2000-05-15
2001-04-24
Wong, Peter S. (Department: 2838)
Electric power conversion systems
Current conversion
Using semiconductor-type converter
C363S133000, C318S434000
Reexamination Certificate
active
06222751
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to circuitry for use in motor drivers and, more particularly, to a driver circuit for use with a polyphase DC motor.
BACKGROUND OF THE INVENTION
Polyphase DC motors are used in applications, such as disk drives of personal computers, where a high accuracy in position and speed control is required. Such motors are controlled by phase commutation, i.e. by switching off the current on one phase while switching on the current on another phase.
A schematic diagram of a typical DC motor system of this kind is shown in FIG.
1
. The system includes a DC motor
12
having a permanent magnet rotor
14
and a stator
16
with three phases
26
a
,
26
b
,
26
c
. A commutator
20
controls the timing and the sequencing of excitation of the three phases in a manner known in the art. Rotor position detectors
103
, such as Hall sensors, optical encoders or sensors of back electromotive force, are used for determining commutation instances. A driver
22
controlled by the commutator
20
and connected to a voltage supply
24
provides current flow to the phases. The phase commutation produces electrical transients due to the inductance of the motor coils. Therefore, torque ripples and other undesirable nonlinearities are generated, which result in acoustical noise produced by the motor, motor wear and electromagnetic interference. To ensure a uniform and noise-free operation the driver must be designed to accurately control the turn-on and turn-off slew-rate at the motor coils during commutation.
A known technique to reduce the electric transients from commutation and thus reduce torque ripple and electromagnetic interference is disclosed in U.S. Pat. No. 5,191,269 assigned to SGS-THOMSON Microelectronics, Inc. In this technique, a current integrator is used to control the gates of field-effect drive transistors in such a manner as to reduce the slew-rate at a stator coil when the drive transistor for that coil is turned off.
An application of such technique is shown schematically in FIG.
2
. Three half-bridge driver circuits
30
a
,
30
b
,
30
c
drive corresponding coils
26
a
,
26
b
,
26
C of a three-phase DC motor connected in the Y configuration. Only one driver circuit is shown in some detail, the other two driver circuits being identical to it. In this example, driver circuit
30
a
has an output stage which comprises two power n-channel MOS field-effect transistors M
1
and M
2
connected as shown between the positive and negative terminals, V
M
and ground, of a power supply. The transistor connected directly to the positive supply terminal, as is M
1
, is usually referred to as the “high-side driver” and the other transistor, connected directly to the negative supply terminal, as is M
2
, is usually referred to as the “low-side driver”. The source of M
1
and the drain of M
2
are connected together at a node OUT which is the output terminal of the driver circuit
30
a
and is connected to stator coil
26
a
. Each transistor M
1
, M
2
has a diode D
1
, D
2
connected between source and drain in the direction of reverse conduction relative to the supply terminals. Typically, transistors M
1
and M
2
are formed on a common semiconductor substrate and diodes D
1
and D
2
are intrinsic diodes. If transistors are used which have no intrinsic diodes, corresponding separate diodes should be provided to implement the current recirculation function, as known to any person skilled in the art. Two operational transconductance amplifiers A
1
, A
2
have their outputs connected to a respective gate terminal of transistors M
1
, M
2
. The non-inverting input of amplifier A
1
and the inverting input of amplifier A
2
are connected to ground. The inverting input of amplifier A
1
is connectable to a constant current generator G
SLEW
through a first electronic switch S
1
and the non-inverting input of amplifier A
2
is connectable to the current generator G
SLEW
through a second electronic switch S
2
. The inverting input of A
1
and the non-inverting input of A
2
are connected to the output node OUT of the output stage
30
a
through a respective capacitor C
1
and C
2
. A sequencer
31
generates switching signals s
1
, s
2
for opening and closing electronic switches S
1
and S
2
, as well as switching signals s
3
, s
4
and s
5
, s
6
for opening and closing corresponding switches in the driver circuits
30
b
,
30
c
, according to a predetermined timing. The sequencer
31
and the electronic switches together form a commutator as shown at 20 on FIG.
1
.
In operation, a current integrating function is provided to reduce voltage transients at node OUT during commutation. These transients are due to the inability to instantaneously change the current through an inductor, such as through stator coils
26
a
,
26
b
,
26
c
. The current integrating function is implemented by current generator G
SLEW
and by capacitor C
1
or C
2
when the corresponding switch S
1
or S
2
is turned on, with the effect of limiting the voltage slew-rate at output node OUT when transistors M
1
and M
2
are alternatively turned off and on.
When the motor current is controlled in the Pulse Width Modulation (PWM) mode, the commutation timing is affected by an appropriate signal as represented at input PWM to sequencer
31
in FIG.
2
. Typically, only the high side drivers (M
1
in
FIG. 2
) are pulse width modulated while the low side drivers (M
2
in
FIG. 2
) are fully switched on or off according to their commutation sequence timing. In this operating mode a problem arises when the voltage at the output node OUT turns from “low” to “high” with outgoing motor current, as shown by an arrow I
Mout
in
FIG. 2
, or from “high” to “low” with incoming motor current, as shown by an arrow I
min
in in FIG.
2
. In this condition a voltage spike appears at the output node which causes perturbances in the supply rails and electromagnetic interference.
To better explain this malfunction reference is made to
FIG. 3
where a portion of the arrangement of
FIG. 2
is represented in a particular operating condition. More particularly, the situation is considered when switch S
1
is turned on and a transition from “low” to “high” must be initiated to cause the motor current to flow from the output node OUT, as shown by arrow I
Mout
. It is important to consider the operating phases which are immediatly preceding this situation. When transistor M
1
is on and transistor M
2
is off, the inductance of coil
26
a
is charged. Transistor M
1
is then switched off while transistor M
2
is still off: this causes output node OUT to go to a voltage lower than ground, which in turn results in diode D
2
to be forward biased and the coil inductance to begin to discharge through the diode. Transistor M
2
is then turned on while transistor M
1
is off: the coil inductance is now discharged through the conducting transistor M
2
more efficiently than through the diode (in fact the power dissipated through M
2
is Ron×I
2
, where Ron is the resistance of transistor M
2
in conduction, and is lower than V
Dfwd
×I, where V
Dfwd
is the voltage across diode D
2
in forward conduction). Next, transistor M
2
is turned off while transistor M
1
is still off. This is the starting condition considered above when the voltage at node OUT should turn from “low” to “high”. It should be noted that in this condition a charge is stored into a parasitic capacitor C
D2
associated to the diode D
2
.
When transistor M
1
starts conducting, current flows not only to the coil
26
a
but also to the capacitor C
D2
which was charged during the previous current flow from the coil inductance to a negative voltage with respect to ground. As soon as capacitor CD
2
is completely discharged, the output node OUT is subjected to a rapid positive voltage transient before the feedback loop comprising capacitor C
1
starts a slew-rate control.
FIGS. 4
a
and
4
b
show plots shows a plot of the voltage V
OUT
at output node OUT as a function of time in two different operating conditions:
FIG. 4
a
) i
Garbelli Luigi Eugenio
Nessi Maurizio
Portaluri Salvatore
Savo Alessandro
Sciacca Giorgio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Laxton Gary L.
STMicroelectronics S.r.l.
Wong Peter S.
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