Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-09-26
2001-09-04
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S108000, C327S423000
Reexamination Certificate
active
06285232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention particularly relates to a driver circuit used for an LVDS interface. In particular, the present invention relates to the driver circuit suitable for stabilizing the output level, and an output stabilizing method therefor.
2. Description of the Related Art
In recent years, an LVDS (low voltage differential signals) interface is given much attention as a fast transmission interface for small amplitude signals. The LVDS is a standard for differential small-amplitude interfaces, which is being advanced by IEEE to be standardized. (refer to “IEEE Standard for Low-Voltage Differential Signals for SCI, LVDS P1596.3 December 1993”).
In this LVDS standard, the output signal of a driver circuit is specified as a differential small-amplitude signal in the order of 1.0 V to 1.4 V. The main characteristic of the driver circuit is that by switching a current path of a predetermined signal current, the driver circuit generates a current flow in an equilibrium transmission line and terminal resistance (100&OHgr;), which are located between a receiver circuit and the driver circuit, and generates a signal voltage between the both terminals of the terminal resistance to transmit the signal.
One of the drawbacks of the conventional LVDS driver circuit is that temperature or process fluctuations cause the output level to shift and fall outside of the specification.
One example of such a driver circuit is shown in FIG.
1
. In the drawing, reference numerals
1
and
6
designate current source transistors, and reference numerals
2
to
5
designate output NMOS transistors for switching signals.
An terminal resistance
9
is connected between output terminals
7
,
8
. The gate of the current source transistor
1
is applied with a bias voltage B
1
which is outputted from a standard voltage circuit
13
.
Inverse signals of the gate signals of the output NMOS transistors
3
,
4
are inputted to the gates of output NMOS transistor
2
,
5
. By the input signals, the current path is switched, and output levels of the output terminals
7
,
8
are generated by the current flow in the terminal resistance
9
.
Also, in order to stabilize the current fluctuation of the current source caused by temperature and process fluctuations, the bias voltage B
1
is generated by the standard voltage circuit
13
to be supplied to the gate of the current source transistor
1
. Also reference numeral
14
in the drawing indicates a borderline between the interior and exterior of a chip or circuit.
One example of the structure of standard voltage circuit
13
is explained here using FIG.
2
. In general, the standard voltage circuit
13
is constructed of a sense amplifier or the like, and has a constant current input terminal
12
and a terminal which is applied with a bias voltage B
1
as external terminals. Also, standard voltage circuit
13
can be constructed of one I/O cell.
By inputting a voltage generated by a constant current inputted from the constant current input terminal
12
and a standard voltage generated by PMOS transistors
15
,
16
to the sense amplifier, the bias voltage B
1
for stabilizing the current is supplied to the current source transistor
1
in FIG.
1
. In the figure, reference numerals
17
,
18
,
19
,
22
designate PMOS transistors, and reference numerals
20
,
21
designate NMOS transistors.
On the other hand, a drain voltage of the current source transistor
1
is inputted to the gate of the current source transistor
6
in FIG.
1
. The amount of current of the current source transistor
1
is controlled by the bias voltage B
1
. The drain voltage of the voltage source transistor
1
is sufficient enough to turn on the current source transistor
6
.
The conventional structure can supply a constant current regardless of the temperature and process fluctuations; however, it cannot sufficiently suppress the output level fluctuations of the ON resistance of the output NMOS transistors
2
to
5
due to the temperature and process fluctuations.
That is, by the process fluctuation, the threshold voltages (Vt) of the output NMOS transistors
2
to
5
may become high. Also, under a high temperature condition, the ON resistance of the current source transistor
1
becomes small as a whole, and the ON resistance of the output NMOS transistors
2
to
5
and current source transistor
6
become large. Therefore, the output level shifts to the power source side (VDD) as a whole, and the center of the amplitude (VOS) also shifts to the VDD side.
Conversely, the conditions such as where Vt becomes lower, or the temperature is low, the ON resistance of the current source transistor
1
becomes larger as a whole, and the ON resistance of the output NMOS transistors
2
to
5
and current source transistor
6
become smaller. Because of this, the output level shifts to the GND side as a whole, and VOS also shifts to the GND side.
FIG. 3
shows the fluctuations of the output HIGH level (VOH), output low level (VOL), and the center of the amplitude (VOS) due to the fluctuations of temperature and process.
The center of the amplitude is defined as VOS=(VOH+VOL)/2, and in the LVDS standard the center of the amplitude is specified as VOS=1.125 to 1.275 (V). Here, when Vt becomes higher caused by the process fluctuation, or under a high temperature condition, the output level shifts to the VDD side as a whole, and VOS shifts to the VDD side as well, resulting in the VOS exceeding the maximum side of the standard.
Conversely, when Vt becomes lower, or under the condition of lowering temperature, the output level shifts to the GND side as a whole, and VOS shifts to the GND side as well, resulting in VOS being lower than the minimum side of the standards.
Therefore, a driver circuit which can control the fluctuations of the output level regardless of the fluctuations of the temperature or the process is in demand.
In order to respond to such a demand, in Japanese Patent Laid-open Publication No. Hei 11-85343, the fluctuations of the output level of the driver circuit due to the temperature or process fluctuation are suppressed by generating bias for the upper and lower current source transistors by means of a returning standard voltage circuit.
That is, as shown in
FIG. 4
, the driver circuit is provided with current source transistors
1
,
6
and output NMOS transistors
2
to
5
. An terminal resistance
9
is connected between the output terminals
7
and
8
. The bias B
1
and bias B
2
are supplied respectively, to the gates of the current source transistors
1
, and
6
from the returning standard voltage circuit
24
.
As shown in
FIG. 5
, the returning standard voltage circuit
24
has a terminal
26
for a HIGH side standard voltage (VH) which is applied externally, a terminal
29
for a LOW side standard voltage (VL), terminals
27
and
28
which connect a standard resistor
25
, and a terminal which outputs the biases B
1
and B
2
. Between the terminals
27
and
28
, the standard resistor
25
is provided.
The returning standard voltage circuit
24
also has comparators
30
,
31
which input the standard voltages VH and VL. Also, the returning standard voltage circuit
24
has transistors
34
,
35
which generate the output HIGH level, transistors
37
,
38
which generate the output LOW level, and capacitors
32
,
33
which implement a stability thereof.
The returning standard voltage circuit
24
generates a dummy output level for the driver circuit within the returning standard voltage circuit
24
by transistors
34
to
38
. Using this dummy output level as a returning voltage, the returning standard voltage circuit
24
compares the standard voltages VH, VL with them using comparators
30
,
31
. By the comparison result, the returning standard voltage circuit
24
controls biases B
1
and B
2
.
The returning standard voltage circuit
24
provides the current source transistors
1
,
6
shown in
FIG. 4
with bias B
1
and bias B
2
, which stabilize the current of the current sourc
NEC Corporation
Tran Toan
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