Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-08-29
2006-08-29
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000, C327S066000, C327S530000, C315S136000, C315S363000
Reexamination Certificate
active
07098877
ABSTRACT:
A driver circuit that allows high-speed switching when the reference current (I) is small. The driver circuit includes a drive current generation circuit (220) for supplying to a first node (232) a drive current based on a binary data signal (DATA); a current mirror circuit (240) for conducting through a second node (234) a current (mI) having a magnitude of the current flowing through the first node (232), multiplied by a predetermined current mirror ratio (m); and a pre-bias circuit (260) for supplying a first pre-bias current (Ib1) to the first node (232) and supplying a second pre-bias current (Ib2) having a magnitude of the first pre-bias current (Ib1), multiplied by said current mirror ratio (m), to the second node (234).
REFERENCES:
patent: 6266929 (2001-07-01), Hauser
patent: 2002/0044008 (2002-04-01), Kawai et al.
patent: 6 120809 (1994-04-01), None
Masuda Shinji
Sakamoto Hiroshi
Bergere Charles E.
Freescale Semiconductor Inc.
Lewis David L.
Shalwala Bipin
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