Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-08-19
2004-04-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C326S023000, C326S027000, C326S083000
Reexamination Certificate
active
06720803
ABSTRACT:
BACKGROUND
The invention generally relates to a driver circuit.
An output driver circuit may be used for purposes of driving a particular logic signal onto a signal line (a data line of a bus, for example). A component of such a driver is a complementary metal-oxide-semiconductor (CMOS) inverter
1
that is depicted in FIG.
1
. As shown, the CMOS inverter
1
includes an n-channel metal-oxidesemiconductor field-effect-transistor (MOSFET), or “NMOSFET”
3
, and a p-channel MOSFET, or “PMOSFET”
2
. The source terminal of the PMOSFET
2
is coupled to a supply voltage (called “V
DD
”) and the drain terminals of the PMOSFET
2
and the NMOSFET
3
are connected together to form an output terminal
4
that furnishes an output signal (called “V
OUT
”). The source terminal of the NMOSFET
3
, in turn, is coupled to another power supply voltage (called V
SS
) that is lower than the V
DD
supply voltage. The gate terminals of the PMOSFET
2
and the NMOSFET
3
are connected together to form an input node that receives an input signal called V
IN
.
The CMOS inverter operates in the following manner. When the V
IN
voltage is at a logic one voltage level, the NMOSFET
3
conducts to drive the V
OUT
voltage to a logic zero level. In response to the V
IN
input voltage being at a logic zero level, the PMOSFET
2
conducts to drive the V
OUT
voltage to a logic one level. Although in the general operation of the CMOS inverter
1
, one of the transistors is fully activated while the other one is fully deactivated, both transistors conduct significant current during the transition of the CMOS inverter
1
between logical states. For example,
FIG. 2
depicts a drain-source current
5
of the NMOSFET
3
and a source-drain current
6
of the PMOSFET
2
during the transition of the V
IN
input voltage from a logic one state to a logic zero state. In this manner, before time T
0
, the CMOS inverter
1
is in a steady state in which the V
IN
input voltage is at a logic one level to cause the NMOSFET
3
to conduct and the PMOSFET
2
to be deactivated, or not conduct. Thus, before time T
0
, the NMOSFET is on but due to the non-conduction of the PMOSFET
2
has essentially no drain source current
5
. However, at time T
0
, the V
IN
input voltage transitions from the logic one level to a logic zero level. During this transition, the PMOSFET's current
6
and the NMOSFET's current
5
ramps upward to a peak
7
, with both currents
5
and
6
descending downwardly to zero levels after time T
1
. Thus, between times T
0
to T
1
, both the NMOSFET
3
and the PMOSFET
2
are conducting, a state of the CMOS inverter
1
that produces the most power dissipation for the inverter
1
due to the non-zero drain-to-source voltage of the NMOSFET
3
and the non-zero source-to-drain voltage of the PMOSFET
2
. The conduction of the NMOSFET
3
during the transition depicted in
FIG. 2
produces what is called a crowbar current. This crowbar current increases the power dissipation of the CMOS inverter
1
. A similar crowbar current is produced by the conduction of the PMOSFET
2
during the transition of the V
IN
signal from a logic one state to a logic zero state.
Therefore, output driver circuits may have crowbar currents that may cause significant power dissipation. Thus, there is a continuing need for better ways to make an output driver circuit.
REFERENCES:
patent: 4833349 (1989-05-01), Liu et al.
patent: 5025181 (1991-06-01), Farmer
patent: 5355028 (1994-10-01), O'Toole
patent: 5495195 (1996-02-01), Fontana et al.
patent: 5751180 (1998-05-01), D'Addeo
patent: 5760620 (1998-06-01), Doluca
patent: 6169421 (2001-01-01), Bryan et al.
patent: 6225844 (2001-05-01), Fujiwara
patent: 6433602 (2002-08-01), Lall et al.
patent: 6529050 (2003-03-01), Kuo et al.
Lam Tuan T.
Trop Pruner & Hu P.C.
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