Driver circuit

Details Driver circuit Driver circuit

2002-07-05

2003-12-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S111000, C327S112000

Reexamination Certificate

active

06661259

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a driver circuit and, more particularly, to a driver circuit suited for driving a capacitive load.
BACKGROUND OF THE INVENTION
For technical publications related to the present invention, see (1) the specification of Japanese Patent Kokai Publication JP-A-11-119750, and (2) the specification of Japanese Patent Kokai Publication JP-A-2000-338461.
FIG. 13
is a diagram illustrating one example of the structure of a driver circuit in a liquid crystal display device disclosed in the specification of Japanese Patent Kokai Publication JP-A-11-119750. As shown in
FIG. 13
, the driver circuit includes an N-channel MOS transistor
1011
whose source is connected to an input terminal T
1
via a switch
1031
and whose gate and drain are tied together; a switch
1032
connected between the drain of the N-channel MOS transistor
1011
and a high-potential power supply VDD; an N-channel MOS transistor
1012
whose gate is connected in common with the gate of the N-channel MOS transistor
1011
(where the node at the point of connection is represented by V
10
) and whose drain is connected to the high-potential power supply VDD via a switch
1033
; a P-channel MOS transistor
1021
whose source is connected to the input terminal T
1
via a switch
1041
and whose gate and drain are tied together; a switch
1042
connected between the drain of the P-channel MOS transistor
1021
and the low-potential power supply VSS; and a P-channel MOS transistor
1022
whose gate is connected in common with the gate of the P-channel MOS transistor
1021
(where the node at the point of connection is represented by V
20
) and whose drain is connected to a low-potential power supply VSS via a switch
1043
. The source of the N-channel MOS transistor
1012
and the source of the P-channel MOS transistor
1022
are connected in common and to an output terminal T
2
. The driver circuit further includes preliminary charging/discharging means constituted by a switch
1044
connected between the output terminal T
2
and the high-potential power supply VDD and a switch
1034
connected between the output terminal T
2
and the low-potential power supply VSS.
FIG. 14A
is a timing chart illustrating the operation for controlling the switches in the conventional driver circuit of
FIG. 13
, and
FIG. 14B
is a diagram illustrating the voltage waveforms of the internal nodes V
10
, V
20
and output voltage Vout of the conventional driver circuit of FIG.
13
.
The operation for controlling the switches of the conventional driver circuit will be described with reference to FIG.
13
and
FIGS. 14A
,
14
B.
First, at time t
0
, the switches
1032
and
1034
are turned on to establish a precharging mode, as a result of which the output voltage Vout declines. Since the switches
1031
and
1032
are off and on, respectively, under these conditions, the bias voltage at the gates of the transistors
1011
and
1012
is the power supply voltage VDD.
Next, at time t
1
, the switches
1031
and
1032
are turned on and off, respectively. As a result, owing to the action of the transistor
1011
, the bias voltage changes to a voltage shifted from an input voltage Vin by an amount equivalent to a threshold value Vth
1011
of the transistor
1011
. Specifically, the bias voltage V
10
is represented by the following equation:
V
10
=
Vin
+Vth
1011
It should be noted that the threshold value Vth of the transistor is represented by a potential for which the source is the reference.
Next, at time t
2
, the switch
1034
is turned off, the precharging mode ends and the switch
1033
is turned on. Under these conditions, the transistor
1012
acts as a source follower and therefore the output voltage Vout changes to a voltage shifted from the bias voltage V
10
at the gate of the transistor
1012
by an amount equivalent to a threshold value Vth
1012
of the N-channel MOS transistor
1012
. Specifically, the output voltage Vout is represented by the following equation:
Vout
=
V10
-
Vth1012
=
Vin
+
Vth1011
-
Vth1012
If Vth
1011
≈Vth
1012
holds, then Vout≈Vin will hold and the output voltage Vout will become approximately equal to the input voltage Vin.
At time t
0
′ (=t
3
), the switches
1042
and
1044
are turned on to establish the precharging mode, as a result of which the output voltage Vout rises. Since the switches
1041
and
1042
are off and on, respectively, under these conditions, the bias voltage at the gates of the transistors
1021
,
1022
is the power supply voltage VSS.
Next, at time t
1
′, the switches
1041
and
1042
are turned on and off, respectively. As a result, owing to the action of the transistor
1021
, the bias voltage changes to a voltage shifted from the input voltage Vin by an amount equivalent to a threshold value Vth
1021
of the transistor
1021
. Specifically, the bias voltage V
20
is represented by the following equation:
V
20
=
Vin+Vth
1021
Next, at time t
2
′, the switches
1044
and
1043
are turned off and on, respectively, and the precharging mode ends. Under these conditions, the transistor
1022
acts as a source follower and therefore the output voltage Vout changes to a voltage shifted from the bias voltage V
20
at the gate of the transistor
1022
by an amount equivalent to a threshold value Vth
1022
of the transistor
1022
. Specifically, the output voltage Vout is represented by the following equation:
Vout
=
V20
-
Vth1022
=
Vin
+
Vth1021
-
Vth1022
If Vth
1021
≈Vth
1022
holds with regard to the threshold voltages of the P-channel MOS transistors
1021
and
1022
, then Vout≈Vin will hold and the output voltage Vout will become approximately equal to the input voltage Vin. It should be noted that in the case of an actual process for manufacturing a LSI chip, there are instances where the threshold voltage of a MOS transistor exhibits some variation. However, by forming the transistors
1011
,
1012
,
1021
,
1022
close to one another and in the same size in the integrated circuit,
Vth
1011
≈Vth
1012
, Vth
1021
≈Vth
1022
can be realized with comparative ease. Thus, the output voltage Vout can be made equal to the input voltage Vin and a data line DL can be driven with a high current supply capability owing to the source-follower action of the transistors.
This driver circuit is such that the transistors
1012
and
1022
function as source followers and little power is consumed because current other than that necessary for charging and discharging does not flow. However, it is difficult to drive the output voltage Vout to a voltage equal to the input voltage Vin rapidly. The reason for this is that in a transistor source-follower operation, most actual transistors have such a characteristic that the current driving capability varies gently while gradually decreasing when the gate-source voltage approaches the threshold voltage, as a result of which an extended period of time is required for the gate-source voltage to reach the vicinity of the threshold voltage and stabilize in the source-follower operation.
FIG. 15
is a diagram illustrating a driver circuit described in the specification of Japanese Patent Kokai Publication JP-A-2000-338461 (see
FIG. 9
in the same specification). By controlling current in a source-follower driver circuit, it is possible to achieve rapid drive and produce a highly precise voltage output.
As shown in
FIG. 15
, this conventional driver circuit includes the N-channel MOS transistor
1011
whose source is connected to the input terminal T
1
via the switch
1031
and whose gate and drain are tied together; a current source
1013
(current I
11
) connected between the drain of the N-channel MOS transistor
1011
and the high-potential power supply VDD; the N-channel MOS transistor
1012
whose gate is connected in common with the gate of the N-channel MOS transistor
1011
and whose drain is connected to the high-potential power supply VDD via the switch
1033
; the switch
1032
connected between the common gates of the N-channel

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