Driver circuit

Details Driver circuit Driver circuit

1982-03-25

1984-04-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307482, 307578, 307581, H03K 301, H03K 17687

Patent

active

044437153

ABSTRACT:
An MOS FET inverter driver circuit. A first FET of the depletion type, a resistance formed by a depletion type FET having its gate connected to its drain, and a second FET of the enhancement type are connected in series between a positive voltage source and ground. Third and fourth FET's both of the enhancement type are also connected in series between the voltage source and ground. The gates of the first, second, and fourth FET's are connected directly to an input terminal. The gate of the third FET is connected to the juncture of the resistance FET and the second FET. A capacitance is connected between the juncture of the resistance FET and the first FET and the juncture of the third and fourth FET's, an output terminal is also connected to this juncture. The circuit obtains bootstrap action by virtue of the capacitance to provide high voltage drive to turn the third FET, the output pull-up transistor, on. The direct connection from the input terminal to the gates of the first, second, and fourth FET's further contributes to high speed operation of the circuit.

REFERENCES:
patent: 4176289 (1979-11-01), Leach et al.
patent: 4395644 (1983-07-01), Misaizu
Chan, J. Y. et al., "A 100 ns 5V Only 64K .times. 1 MOS Dynamic RAM," IEEE Journal of Solid-State Circuits, vol. SC-15, No. 5, pp. 839-846, 1980.

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