Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-01-19
2004-01-06
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S534000, C345S535000, C345S564000
Reexamination Certificate
active
06674423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a drive unit and a liquid crystal device using the same drive unit. More particularly, the invention relates to a drive unit having a memory for storing display data from a microprocessor unit and to a liquid crystal device using the same drive unit.
2. Background Art
So far, as a signal line driver (drive unit) applicable to liquid crystal device, there has been known a signal line driver which internally incorporates a memory for storing display data. The use of this signal line driver enables display of an image through the use of display data in a built-in memory without transferring display data from an external microprocessor unit (which will hereinafter be referred to suitably as an MPU) on occasion; therefore, the power consumption is considerably reducible in display of static images.
In connection with such a memory-incorporated signal line driver (column driver), there exists an MPU access request (first access request) forming a request for access to a memory according to a command from an MPU and an LCD access request (second access request) forming a request for access to a memory according to a displaying operation in an LCD (displaying section). Additionally, the LCD access request takes place in synchronism with periodic timings for liquid crystal display, while the MPU access request is made in asynchronous relation to the liquid crystal display timings. For this reason, there is a possibility that these access requests take place competitively.
One possible solution to such a competition between the access requests is use of a dual-port memory as an incorporated memory of a signal line driver. This dual-port memory has two data ports which are accessible simultaneously. Accordingly, even if the competition between access requests comes about, the read/write operation is achievable properly in the memory.
However, the cell size of such a dual-port memory is extremely larger than that of a single-port memory; in consequence, the use of the dual-port memory as an incorporated memory enlarges a chip area of the signal line driver, thereby increasing the price of the signal line driver.
Meanwhile, as a conventional means utilizing a single-port memory but capable of eliminating the problem in a competition between access requests through contrivance of circuit arrangement, there has been known a technique disclosed in Japanese Unexamined Patent Publication No. 10-105505.
There is a problem arising with this conventional technique, however, in that, when the sum of a processing time of an access operation according to an MPU access request and a processing time of an access operation according to an LCD access request is taken as T, there is a need to set the interval in time between MPU access requests at T, not only at a competition between access requests but also in a non-competitive condition. Hence, difficulty is experienced in realizing high-speed data transfer from an MPU to a signal line driver, and a burden imposed on the MPU increases.
In addition, as conventional techniques regarding a signal line driver incorporating a memory, there have been techniques disclosed in Japanese Unexamined Patent Publication Nos. 10-106254 and 10-105120.
For example, Japanese Unexamined Patent Publication No. 10-106254 discloses a signal line driver capable of rewriting display data in a specified display area.
However, this conventional technique requires that an MPU issues a return command or a writing start command whenever a write address goes beyond an address range in a specified display area, thus leading to an increase in processing load imposed on the MPU. Specifically, in a case in which a liquid crystal display panel has a large screen, this problem becomes serious.
Furthermore, Japanese Unexamined Patent Publication No. 10-105120 discloses the conventional technique in which a monitor circuit monitors whether or not data is read from or written in a memory and, if the read/write thereof is not made from/in the memory, a terminal of an input/output circuit is set at a high-impedance condition.
However, this conventional technique, for its own object, uses only one chip select signal to set an input terminal of an input/output circuit to a high-impedance condition, but it does not achieve an object on speed-up of data transfer or reduction of processing load on an MPU.
SUMMARY OF THE INVENTION
The present invention has been developed in consideration of the aforesaid technical objects, and it is an object of the invention to provide a drive unit and a liquid crystal device which are capable of responding exactly to a first access request from a microprocessor side and a second access request from a displaying section side, and further of realizing a high-speed operation and a low-power-consumption operation.
For this object, in accordance with this invention, there is provided a drive unit which receives display data from a microprocessor unit to drive a displaying section, characterized by comprising a memory for storing display data to be used for image display in the displaying section, an arbitration circuit for receiving a first access request forming a request for access to the memory according to a command from the microprocessor unit and a second access request forming a request for access to the memory according to a displaying operation in the displaying section to arbitrate in priority between the first and second access requests for starting an access operation to the memory according to the preferential one of the first and second access requests, and a circuit for outputting, to an external terminal, a memory access monitor signal for monitoring an access condition of the memory to which an access operation starts in accordance with the arbitration of the arbitration circuit.
According to this invention, upon receipt of the first and second access requests, the arbitration circuit arbitrates in the priority between the first and second access requests. When giving the priority to the first access request, the arbitration circuit starts an access operation according to the first access request. On the other hand, when giving the priority to the second access request, it starts an access operation according to the second access request.
In addition, according to this invention, a memory access monitor signal is outputted to an external terminal of the drive unit for monitoring an access condition to the memory. Accordingly, by means of the measurement of a signal level of this memory access monitor signal or variation timing of the signal level, information as to what arbitration is conducted in the arbitration circuit is obtainable through monitoring from the external. In consequence, for example, it is possible to determine a proper generation timing of the first access request.
Still additionally, this invention is characterized in that, when a competition arises between the first and second access requests, the memory access monitor signal becomes active for at least a processing time for a first access operation according to the first access request plus a processing time for a second access operation according to the second access request. In this way, for example, the determination of a proper generation timing of the first access request or the like becomes feasible by merely measuring the length of time for which the memory access monitor signal is active.
Moreover, this invention is characterized in that the memory access monitor signal is a signal to be outputted through the aforesaid external terminal to a wait terminal of the microprocessor unit. This can prolong the time interval between the first access requests only when a competition between the first and second access requests takes place, while it can shorten the time interval therebetween in the normal condition, thus accomplishing a high-speed data transfer.
Still moreover, this invention is characterized by comprising a first control circuit for outputting a signal indicative of the first acc
Epson Corporation
Hogan & Hartson LLP
Liang Regina
Nguyen Francis
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