Drive unit and display module including same

Details Drive unit and display module including same Drive unit and display module including same

2007-01-02

2007-01-02

Hjerpe, Richard (Department: 2629)

Computer graphics processing and selective visual display system

Display driving control circuitry

C345S087000, C345S098000, C345S100000

Reexamination Certificate

active

10172972

ABSTRACT:
A data latch circuit in a source driver has delayed flip-flops (DFFs) which receive display data signals R·G·B, in synchronism with respective rising and falling edges of a clock signal SCK having a half frequency of the display data signals R·G·B. Furthermore, the OFFs independently output to a sampling memory circuit the display data signals R·G·B received in synchronism with the rising edge of the clock signal SCK and the display data signals received in synchronism with the falling edge of the clock signal SCK.

REFERENCES:
patent: 5734378 (1998-03-01), Okada et al.
patent: 5856816 (1999-01-01), Youn
patent: 6229513 (2001-05-01), Nakano et al.
patent: 2002/0080107 (2002-06-01), Fujimoto et al.
patent: 06-95618 (1994-04-01), None
patent: 10-161600 (1998-06-01), None
patent: 2000-305530 (2000-11-01), None

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