Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2005-04-19
2005-04-19
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
06882329
ABSTRACT:
A drive signal generation circuit which performs gradation control on a load by a drive signal having a stepped waveform. In a case where the wave height value corresponding to input gradation data is Vm (2≦m≦n), the drive signal is caused to rise in such a manner that each output Vk (2≦k≦m) is produced one slot after the output V(k−1) to increase the wave height value V0(reference potential) to Vm in a stepping manner. One slot corresponds to a unit time of the pulse width modulation. The drive signal is caused to fall in such a manner that each output V(k−1) (1≦k≦m−1) is produced one or two slots after the output Vk to reduce the wave height value from Vm to off level in a stepping manner. A delay circuit is used to delay signals slot by slot. A selection is made from delayed signals according to luminance data to determine a waveform. The circuit is also designed to enable the drive signal waveform rise position to be changed.
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Aoki Tadashi
Isono Aoji
Murayama Kazuhiko
Sakamoto Tsutomu
Shino Kenji
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Patel Nitin
Shalwala Bipin
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