Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-01-30
2003-01-07
Nguyen, Matthew (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06504353
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a semiconductor memory device and, more particularly, to a semiconductor device having an internal supply voltage generating circuit that provides internal circuits with an internal supply voltage.
A semiconductor memory device has two internal supply voltage generating circuits for generating internal supply voltages supplied to the individual internal circuits in order to reduce the consumed current in standby mode and self-refresh mode. The first internal supply voltage generating circuit (voltage-drop circuit for large power, which will hereinafter be referred to as “large-power voltage-drop circuit”) consumes a relatively large current and supplies relatively large drive power. The second internal supply voltage generating circuit (voltage-drop circuit for small power, which will hereinafter be referred to as “small-power voltage-drop circuit”) consumes a relatively small current and supplies relatively small drive power. In the active mode of the semiconductor memory device, the first and second internal supply voltage generating circuits operate to supply internal supply voltages to the individual internal circuits. In standby mode or power-down mode, the first internal supply voltage generating circuit stops operating and the second internal supply voltage generating circuit alone operates to supply the internal supply voltage to the individual internal circuits. The operation of only the second internal supply voltage generating circuit reduces the consumed power of the semiconductor memory device.
In standby mode or power-down mode, when current stops flowing in all of the internal circuits (load circuits), which are connected to the first and second internal supply voltage generating circuits via power lines, the potential of the power lines rises as a result of the transistor characteristic (sub-threshold characteristic) of the internal supply voltage generating circuits.
When the mode is changed from standby or power-down to active mode, an internal supply voltage exceeding a set value is supplied to the internal circuits, thereby altering the device characteristics. As a cell-plate voltage generating circuit or a self-refresh oscillation circuit connected to the power lines consumes power in standby mode or power-down mode, however, the rise in internal supply voltage is suppressed.
Because of various factors related to the microfabrication process, such as problems with maintaining voltage, excessive power consumption, power supply noise, the set level of the voltage-drop potential, and the use of external interfaces, there is a tendency to use separate internal supply voltage generating circuits for inputs and outputs, peripheral function circuits, and memory arrays. In such a configuration, without a load circuit (internal circuit)operating in standby mode or power-down mode and connected to the internal supply voltage generating circuit for inputs and outputs, the internal supply voltage rises.
If a load circuit is connected to the internal supply voltage generating circuits for the input/output circuits and the memory array, the load circuit stops operating in standby mode, causing the internal supply voltage to rise. In the case of a memory array, an internal circuit, such as a sense amplifier, generates a self-refresh in power-down mode. However, the internal circuit, which has an operation time of tens of nanoseconds, operates only once in several tens of microseconds, on average. The operational ratio is therefore about 1/1000. As a result, the internal supply voltage rises.
A semiconductor memory device has been proposed that is designed to suppress an increase in internal supply voltage. In the device, a leak element (e.g., a resistor, MOS diode, or the like), which does not perform any of the intended functions of the semiconductor memory device, is connected to the power lines of each internal supply voltage generating circuit. A leak current of between several and several hundred &mgr;A continually flows through the leak element, so that a constant current is consumed even in standby mode or power-down mode. This suppresses a rise in internal supply voltage. However, because of the continual flow, consumed power in standby mode or power-down mode inevitably increases.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device that stably retains the internal supply voltage in standby mode or power-down mode and reduces the consumed current.
In a first aspect of the present invention, a drive power supply method for a semiconductor device is provided. The semiconductor device has an internal supply voltage generating circuit. First, first and second internal circuits are connected to the internal supply voltage generating circuit. The first internal circuit is inactivated in standby mode or power-down mode and is activated in active mode. The second circuit operates in the standby mode, the power-down mode and the active mode. Drive power is supplied to the first and second internal circuits from the internal supply voltage generating circuit.
In a second aspect of the present invention, a drive power supply method for a semiconductor device is provided. The semiconductor device has a plurality of internal supply voltage generating circuits, each including a first voltage-drop circuit for supplying relatively large drive power and a second voltage-drop circuit for supplying relatively small drive power. First, first and second internal circuit are connected to at least one of the plurality of internal supply voltage generating circuits. The first internal circuit is inactivated in standby mode or power-down mode and is activated in active mode. The second internal circuit operates in the standby mode, the power-down mode and the active mode. Next, drive power is supplied to the first and second internal circuits from at least the first voltage-drop circuit in the active mode. Drive power is supplied to the second internal circuit from at least the second voltage-drop circuit in the standby mode or the power-down mode.
In a third aspect of the present invention, a semiconductor device is provided that includes at least one internal supply voltage generating circuit for generating relatively small drive power in standby mode or power-down mode and generating relatively large drive power in active mode. A first internal circuit is activated and receives drive power from the at least one internal supply voltage generating circuit in the active mode and is inactivated in the standby mode or the power-down mode. A second internal circuit operates by receiving drive power from the at least one internal supply voltage generating circuit in the standby mode, the power-down mode and the active mode.
In a fourth aspect of the present invention, a semiconductor memory device is provided that includes at least one internal supply voltage generating circuit including a first voltage-drop circuit for generating relatively large drive power and a second voltage-drop circuit for generating relatively small drive power. A first internal circuit is activated and receives drive power from at least the first voltage-drop circuit of the at least one internal supply voltage generating circuit in active mode and is inactivated in standby mode or power-down mode. A normally-driven internal circuit operates by receiving drive power from the second voltage-drop circuit of the at least one internal supply voltage generating circuit in the standby mode, the power-down mode and the active mode.
In a fifth aspect of the present invention, a semiconductor memory device includes a plurality of internal supply voltage generating circuits, each including a first voltage-drop circuit for generating relatively large drive power and a second voltage-drop circuit for generating relatively small drive power. A plurality of first internal circuits, each of which is activated and receives drive power from at least the first voltage-drop circuit
Kato Yoshiharu
Kobayashi Isamu
Fujitsu Limited
Nguyen Matthew
LandOfFree
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