Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-01-08
2008-01-08
Patel, Nitin I. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000
Reexamination Certificate
active
07317442
ABSTRACT:
In a drive circuit of a display apparatus in which a plurality of scanning lines and a plurality of data lines are orthogonalized, a first data latch circuit latches image data for every line in response to a horizontal signal. A decoder circuit decodes the latched image data. A gradation voltage selecting circuit selects voltage lines based on the decoded image data, to connect each of the plurality of data lines with any of the voltages lines. A data determining circuit generates determination signals based on the selected voltage lines such that each of a plurality of gradation amplifiers is selectively set to an inactive state based on the determination signal. A gradation amplifier circuit includes the plurality of gradation amplifiers, each of which amplifies a corresponding one of gradation voltages when being in an active state and does not amplify the corresponding gradation voltage when being in an inactive state, and the amplified gradation voltage being outputted on a corresponding one of the voltage lines. An output circuit drives the plurality of data lines based on the amplified gradation voltages on the voltage lines.
REFERENCES:
patent: 6014122 (2000-01-01), Hashimoto
patent: 7006114 (2006-02-01), Sakaguchi
patent: 2005/0057470 (2005-03-01), Tobita
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Hashimoto Yoshiharu
Nakai Daisaburou
NEC Electronics Corporation
Patel Nitin I.
Sughrue Mion Pllc.
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