Drive circuit for liquid crystal display cell

Details Drive circuit for liquid crystal display cell Drive circuit for liquid crystal display cell

1999-11-08

2002-11-05

Shankar, Vijay (Department: 2673)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S087000

Reexamination Certificate

active

06476785

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to video displays, and more particularly, to a circuit structure for a picture element for use in a liquid crystal display.
BACKGROUND ART
With reference to
FIG. 1
, a typical liquid crystal display consists of an array
11
of picture element
13
, or pixels. Each picture element consists of a select transistor
15
for coupling a column line
17
to a storage capacitor
19
. A liquid crystal
21
is placed in parallel to storage capacitor
19
.
As is known in the art, the voltage potential applied to liquid crystal
21
will determine its reflectivity. In effect, the voltage potential range translates into a gray scale at liquid crystal
21
. Thus by proper application of specific voltage potentials to all picture elements
13
in array
11
, an image may be generated.
Row select box
25
actuates all picture elements
13
within a specific row, which is defined by a row line
27
couple to all select transistors
15
within the row. Video Signal box
23
applies a desired voltage potentials on a column lines
17
. The desired voltage potentials are typically within a predetermined voltage range. The actuation of select transistor
15
transfers a column line's
17
voltage potential to a respective parallel combination of storage capacitor
19
and liquid crystal
21
. Once the desired voltage has been transferred, select transistor
15
is deactivated. The combined capacitance of storage capacitor
19
and liquid crystal
21
sustain the desired voltage potential until the next image is loaded.
Several variations to the basic architecture of
FIG. 1
have been previously proposed. With reference to
FIG. 2
, another liquid crystal architecture, more fully disclosed in U.S. Pat. No. 4,870,396 to Shields, attempts to improve the average RMS voltage potential applied to each liquid crystal
21
. All elements in
FIG. 2
similar to those of
FIG. 1
are identified with similar reference characters and are explained above.
Each picture element
13
in
FIG. 2
is capable of displaying its current contents while simultaneously receiving a new data image. This is done by means of an additional switch, load transistor
29
, which is inserted between storage capacitor
19
and liquid crystal
21
. In operation, select transistor
15
and load transistor
29
function as a bucket brigade transferring charge first from column line
17
to storage capacitor
19
, and then from storage capacitor
19
to liquid crystal
21
. In other words, select transistor
15
first transfers a voltage potential from column line
17
to storage capacitor
19
during a first phase of operation. During this phase of operation, load transistor
29
is maintained turned off and thereby isolates storage capacitor
19
from liquid crystal
21
. Once new data has been loaded unto storage capacitor
19
and is ready to be displayed, a second phase of operation begins with select transistor
15
being turned off. At this time, load transistor
29
is turned on and couples storage capacitor
19
to liquid crystal
21
. The charge across storage capacitor
19
redistributes itself across the parallel combination of storage capacitor
19
and liquid crystal
21
. When the distributing charge has established a new voltage potential across liquid crystal
21
, the second phase of operation ends with load transistor
29
being turned off. While load transistor
29
is turned off and liquid crystal
21
is holding its current voltage potential, select transistor
15
may be actuated and new data transferred from column line
17
to storage capacitor
19
.
Shields explains that in order to improve the average RMS voltage value applied to array
11
, one needs to control the reference voltage Vtp applied to liquid crystals
21
and to update all picture elements
13
in array
11
simultaneously. Reference voltage Vtp is coupled to the reference plate of all liquid crystals
21
. By shifting reference voltage Vtp from one voltage power rail to another, as appropriate, one can increase the average voltage magnitude applied across array
11
.
To this end, load transistors
29
are all controlled by a common synchronization signal
31
. While load transistors
29
are turned off and liquid crystals
21
are holding their current voltage potential, storage capacitors
19
receive new data. Once the entire array
11
has received new data, synchronization line
31
is actuated and all load transistors
29
of all picture elements
13
in array
11
are turned on in unison. Thus, the entire array
11
of liquid crystals
21
is updated simultaneously.
With reference to
FIG. 3
another array architecture, similar to that of
FIG. 2
, is shown. All elements in
FIG. 3
similar to those of
FIG. 2
are identified by similar reference characters and are. explained above. The architecture of FIG.
3
. is more fully disclosed in U.S. Pat. No. 5,666,130 to Williams et al., and is assigned to the same assignee as that of FIG.
2
. The structure of
FIG. 3
updates an entire array
11
of pixels
13
simultaneously, in a manner similar to that of FIG.
2
.
Unlike the structure of
FIG. 2
, however, the structure of
FIG. 3
cannot display one image while storing another. Williams et al. explain that traditionally one has to optimize a pixel's drive circuitry to the specific type of screen, i.e. liquid crystal, being used. Williams et al. state that it would be advantageous to be able to optimize a pixel's drive circuitry separately from the type of liquid crystal used so that one driver circuit could be used with multiple types of screens.
To accomplish this, the structure of Williams et al. allow for an array
11
of picture elements
13
to receive and store an image in their respective storage capacitor
19
while maintaining the storage capacitor
19
isolated from the liquid crystal itself. In this manner, the driver circuitry of each picture element
13
may be optimize for storing an image element, i.e. voltage potential, at a respective storage capacitor
19
with no concern as to the type of liquid crystal
21
used. Once an image has been stored onto the array's storage capacitors
19
, the storage capacitors
19
may be coupled to any screen type and their content, i.e. image voltage, is transferred onto the screen's liquid crystals
21
. To assure that the optimized drive circuitry functions similarly on different types of liquid crystals, Williams et al. demonstrate that the liquid crystals
21
and storage capacitors
19
should be in a known reference ground condition before a new image is loaded. Thus, a current image must first be erased, i.e. array
11
is grounded, before a new image can be received.
The picture elements
13
shown in
FIG. 3
are similar to those of
FIG. 2
with the addition of a grounding transistor
31
between load transistor
29
and liquid crystal
21
. Grounding transistor
31
is responsive to a reinitiate signal, ReInit, which grounds storage capacitor
19
and liquid crystal
21
in preparation for receiving a new image.
After storage capacitor
19
and liquid crystal
21
are grounded, grounding transistor
15
is deactivated and picture element
13
is then ready to receive new voltage data. Row select box
25
activates a row of picture elements
13
by actuating a row's select transistors
15
. Select transistors
15
then transfer new voltage information from the video signal box
23
and column lines
17
to storage capacitors
19
. Once new data has been placed on storage capacitors
19
, load transistors
29
couple storage capacitors
19
to liquid crystals
21
. Grounding transistors
31
are maintained in off state during this time. After liquid crystals
21
have displayed the image for a predetermined period, grounding transistors
31
are turned on while load transistors
29
are maintained actuated. This reinitiates storage capacitors
19
and liquid crystals
21
back to a known grounding state in preparation for loading of the next image.
Williams et al. state that their array can be made more

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