Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-10-03
2006-10-03
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S096000, C345S098000, C345S204000
Reexamination Certificate
active
07116300
ABSTRACT:
Specified thin-film transistors26and27are caused to conduct by a gradation signal inputted in control circuits24and25, and resistors with a conduction resistance of activated transistors are inserted between any of reference voltages V0, V2, and V4and an output terminal T1or between any of reference voltages V1and V3and an output terminal T2, and a pair of thin-film transistors29in a sampling circuit23are caused to conduct simultaneously in sync with the gradation signal. If a signal line SL1is selected, reference voltages V0, V2, or V4and V1or V3are applied to the signal line SL1, either as they are or as divided by the conduction resistance of the activated thin-film transistors, by using a junction point between the sampling circuit23and signal line SL1as a voltage dividing point.
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Akimoto Hajime
Kageyama Hiroshi
Mikami Yoshiro
Dickstein & Shapiro LLP
Hitachi , Ltd.
Hjerpe Richard
Shapiro Leonid
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