Drive circuit and drive circuit system for capacitive load

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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C327S112000, C326S083000

Reexamination Certificate

active

06624669

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a drive circuit and a drive circuit system, and more specifically to a drive circuit and a drive circuit system used in a driver or a buffer which constitutes an output stage of a driving circuit for a capacitive load exemplified by a liquid crystal display (LCD).
As a typical example of a drive circuit for a capacitive load, a liquid crystal display (LCD) will be now described. In general, a display section of the liquid crystal display of an active matrix driving type includes a semiconductor substrate having transparent pixel electrodes and thin film transistors (TFT) formed thereon, an opposing substrate having a single transparent common electrode formed to cover the whole of a surface of the substrate, and a liquid crystal encapsulated between the two substrates which are located to oppose each other, separately from each other. By controlling the TFTs having a switching function, a predetermined voltage is applied to selected pixel electrodes so that a transmittance of the liquid crystal is changed by a potential difference between each pixel electrode and the opposing common electrode.
On the semiconductor substrate, data lines for supplying a plurality of different level voltages (gradation voltages) to be selectively applied to each pixel electrode, and scan lines for supplying a switching control signal for each TFT, are located. The data lines become a large capacitive load because of a liquid crystal capacitance between the data lines and the opposing common electrode and a capacitance between the data lines and the scan lines that intersect each other. Since the gradation voltage is applied through the data line to each pixel electrodes, and since the gradation voltages are written to all the pixels connected to the data lines during each one frame period, a data line drive circuit has to rapidly drive a corresponding data line which is a large capacitive load.
As mentioned above, the data line drive circuit is required to rapidly drive a corresponding data lines having a large capacitance with a high voltage precision. In order to meet with this demand, various data line drive circuits have been developed. Of the various data line drive circuits developed until now, a circuit that has enabled a high voltage precision output and a rapid driving is a drive circuit including a driver (buffer) section formed of an operational amplifier. A typical and simplest example will be shown in FIG.
16
.
The operational amplifier shown in
FIG. 16
is in the form of a voltage follower, capable of outputting, as an output voltage Vout, a voltage equal to an input voltage Vin. The shown operational amplifier is constituted of a differential amplifier stage
610
and an output amplifier stage
620
. The differential amplifier stage
610
includes a current control circuit
601
, PMOS transistors
603
and
604
having the same characteristics, and NMOS transistors
605
and
606
having the same characteristics, which are connected as shown.
In brief, the NMOS transistors
605
and
606
have respective gates connected in common, and respective sources connected in common to a power supply terminal T
14
. A drain of the NMOS transistor
606
is connected to the gate of the NMOS transistor
606
. The PMOS transistors
603
and
604
have respective sources connected in common. A gate of the PMOS transistor
603
is connected to an input terminal T
1
to receive the input voltage Vin. A drain of the PMOS transistor
603
is connected to a drain of the NMOS transistor
605
. A gate of the PMOS transistor
604
is connected to an output terminal T
2
for outputting the output voltage Vout.
A drain of the PMOS transistor
604
is connected to the drain of the NMOS transistor
606
. The current control circuit
601
is connected between a power supply terminal T
13
and the common-connected sources of the PMOS transistors
603
and
604
.
On the other hand, the output amplifier stage
620
includes a current control circuit
602
, an NMOS transistor
607
and a capacitor
608
, connected as shown. The current control circuit
602
is connected between a power supply terminal T
11
and the output terminal T
2
. The NMOS transistor
607
has a drain connected to the output terminal T
2
, a source connected to a power supply terminal T
12
, and a gate connected to the common-connected drains of the PMOS transistor
603
and the NMOS transistor
605
. The capacitor
608
is connected between the gate of the NMOS transistor
607
and the output terminal T
2
. Here, currents controlled by the current control circuits
601
and
602
are called I
61
and I
62
, respectively. A voltage V
DD
is supplied to the power supply terminals T
11
and T
13
, and a voltage V
SS
is supplied to the power supply terminals T
12
and T
14
. In addition, the output terminal T
2
is connected to the data line, which is a capacitive load.
Since the output voltage Vout is fed back to the differential amplifier stage
610
, namely, since the output voltage Vout is applied to the gate of the PMOS transistor
604
, the operational amplifier shown in
FIG. 16
has a construction having a voltage amplification factor of “1” (one) and a high current supplying capacity (voltage follower).
In operation, when the output voltage Vout is lower than the input voltage Vin, a gate voltage of the NMOS transistor
607
is lowered, so that the NMOS transistor
607
is temporarily brought into an off condition, with the result that the output voltage Vout is pulled up by the current I
62
supplied through the current control circuit
602
. On the other hand, when the output voltage Vout is higher than the input voltage Vin, a gate voltage of the NMOS transistor
607
is elevated, so that the output voltage Vout is pulled down by action of the NMOS transistor
607
. At this time, since the NMOS transistors
605
and
606
act to flow the same current through the respective drain-source paths, the output voltage Vout is attenuated and rapidly converged to the input voltage Vin. In the operation, a phase compensation is carried out by the capacitor
608
so that oscillation is prevented.
In the above mentioned operation, a designated or selected gradation voltage is applied as the input voltage Vin during each outputting period, and the operational amplifier can drive the data line connected to the output terminal T
2
and having a large capacitance, by the gradation voltage with a high current supplying capacity.
In addition, the operational amplifier can drive the data line, by action of an impedance conversion, independently of a current supplying capacity of an external circuit supplying the input voltage Vin.
However, since the operational amplifier shown in
FIG. 16
(voltage follower circuit) has a feed-back structure, oscillation often occurs, and therefore, it is necessary to provide the means such as a phase compensation capacitor for preventing the oscillation. Furthermore when the operational amplifier is integrated as an integrated circuit, the phase compensation capacitor often requires a large occupying chip. Therefore, when a number of operational amplifiers are built in a single integrated circuit, a required area of the integrated circuit becomes large, with the result that a production cost adversely increases.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a drive circuit having a simple circuit construction which can be constituted of only transistors, and capable of stably operating with no oscillation, for rapidly driving a load with a high precision voltage output.
Still another object of the present invention is to provide a drive circuit and a drive circuit system, which can reduce the production cost when a number of drive circuits are integrated as an integrated circuit.
The above and other objects of the present invention are achieved in accordance with the present invention by a drive circuit

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