Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
1998-11-13
2002-01-15
Nguyen, Phu K. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
Reexamination Certificate
active
06339424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a drawing processor to process, display, and output image data generated by a computer.
2. Description of the Related Art
When image data generated by a computer is processed to be displayed on a screen or outputted to a printer, since the processing of color image data specially takes a long time, devices to accelerate the processing have been added in the conventional technique. The devices perform functions such as a compression expansion processing to make a color image compact, rotation and enlargement processing for edition, vector operation to calculate coordinate values, color compensation to enhance picture quality, and filtering. These additional devices are generally called the hardware accelerators. Use of these hardware accelerators will achieve a higher rate in processing than in processing by use of the operation processor of a computer with software. The disadvantage of the hardware accelerators lies in that all the functions desired to be accelerated have to be prepared by hardware. Though it depends on the number of functions to support, basically the circuit size becomes greater. In the case of a printer, for example, the foregoing hardware accelerators become necessary in addition to other than the hardware to implement essential processing functions such as interpretation of the page description language (PDL) file, expansion of images, and operation of the printer as well as monitoring of the normal end.
In regard to this, the Japanese Published Unexamined Patent Application No. Hei 06-131155 proposes a device, in which programmable logic is used in an address generator block and an operation block, and modified data of various image processing are stored as a file, thereby common programmable logic is modified to comply with various image processing.
Further, the Japanese Published Unexamined Patent Application No. Hei 06-282432 proposes a device, in which data flows as to combinations of operation circuits for various processing corresponding to various processing are controlled, and thereby various processing is executed with less combinations of operations, which reduces the scale of operation circuits.
However, these conventional methods involve many restrictions in performing image processing, and they cannot sufficiently utilize the circuit scale. The processing method that resisters macro processing groups necessary for specific image processing in the operation processor, temporarily decodes instruction codes inputted from outside, generates addresses, and selects operations, is effective when the processing consists of sets of simple processing. However, the method is not effective in implementing complicated and various types of processing. Installation of a plurality of arithmetic logic units (ALU) to implement parallel processing effects an improvement. However, the serial processing is suited to the pipeline processing in the image processing, and the parallel processing exhibits a higher rate than versatile programs, and yet the hardware accelerators do not demonstrate a sufficient effect for its scale.
And, these techniques support a part of the image processing other than the essential processing, which however does not make the device compact as a whole.
SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing problems of the conventional techniques, and an object of the invention is to provide a construction whereby both the essential function of the image processing and the accelerator function to exceptionally accelerate processing of a heavy load can be implemented by hardware, and the hardware can be made up on a small circuit scale.
In order to accomplish the foregoing object, the drawing processor according to the invention is formed of hardware, and it is provided with a real-time path unit that processes synchronously with the image processing rate of the output device, a non-real-time path unit that processes at a lower rate than the synchronized rate, and a path determination unit that determines whether the inputted image data is transferred to the real-time path unit or to the non-real-time path unit, on the basis of the content of the inputted image data. And the drawing processor is constructed such that the non-real-time path unit at least contains rewritable hardware that reconfigures processing functions.
In this construction, since the non-real time processing is implemented by the reconfigurable hardware, the same hardware is able to execute various kinds of non-real time processing, whereby the circuit scale can be kept small. Further, high-speed processing becomes possible compared to the processing executed with software.
The present invention will further be described in detail. One example of the system that is implemented by the present invention is comprised of an operation processor, an integrated drawing processor, and an output device as a whole. The integrated drawing processor is composed of an operation processor interface (I/F), a real-time path unit, a non-real-time path unit, and an output device I/F. The operation processor I/F is formed of an input buffer and a path determination unit. The non-real-time path unit is composed of a reconfiguration data control unit, reconfigurable hardware, a work memory, and an output buffer. Attached to the data transferred from the operation processor is header information as to the designation of the real-time path unit or the non-real-time path unit, and the parameters. And, if an ID number is attached to the header, the reconfiguration data control unit loads processing logic into the reconfigurable hardware to bring it into function based on the ID number. A path switch switches the path, whereby the reconfigurable hardware sitting in the non-real-time path unit can also be used in the real time path.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the present invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 4775946 (1988-10-01), Anjyo
patent: A-6-13115 (1994-05-01), None
patent: A-6-282432 (1994-10-01), None
Ishikawa Hiroshi
Kawata Tetsuro
Fuji Xerox Co. LTD
Nguyen Phu K.
Oliff & Berridg,e PLC
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