Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2000-11-13
2004-05-25
Ahmed, Samir (Department: 2623)
Image analysis
Applications
Manufacturing or product inspection
C382S144000, C716S030000
Reexamination Certificate
active
06741733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a drawing pattern verifying method for verifying a drawing pattern of a mask for drawing a circuit pattern as a set of fine patterns of a semiconductor device and, more particularly, to a drawing pattern verifying method by use of partial or overall batch transfer employing a stencil mask.
The present application claims priority of Japanese Patent Application No. Hei11-323382 filed on Nov. 12, 1999, which is hereby incorporated by reference.
2. Description of the Related Art
There is put to practical use such a micro-lithography technology that, in steps of manufacturing semiconductor devices, utilizes a focused beam of such a charged particle beam as an electron beam (EB), ion beam, or a like, in order to draw integrated circuit patterns. For example, by one of such technologies, a relevant electron beam exposure apparatus applies the electron beam to a wafer coated with an electron beam-sensitive resist to directly project integrated circuit patterns to the wafer, by using an EB mask in order to obtain a required drawing pattern by use of the electron beam. Such an electron beam drawing technology by use of the electron beam comes in a partial batch exposure method or an overall batch exposure method, by either of which a mask pattern is reduced and projected to a give batch drawing of unit regions such as a memory cell. These two methods both use two masks usually, to shape the electron beam into a rectangular one by using a first mask and then apply this rectangular electron beam to a second mask. The second mask previously has a plurality of rectangular cell apertures on which is formed a partial pattern cut out of a drawing pattern to be projected to a wafer, so that these cell apertures are reduced several ten-fold through an electric optical system and then transferred to the wafer in batch exposure. These partial and overall batch exposure methods are superior to the variable shaped beam approach not only in a respect of an improved throughput due to a decrease in a number of projections required but also in a respect of such improvements in inter-projection connecting accuracy, slant pattern image quality, and pattern data compressibility that, for example, may have no direct influences on wafer drawing time even with finer patterning.
In addition, there is available as a lithography apparatus employing the ion beam such the ion beam transfer exposure apparatus, by which the mask pattern is projected in transfer to the wafer using the ion beam like the electron beam lithography apparatus. This method can provide batch projection of all chip patterns in transfer by using the ion beam to realize a higher throughput while maintaining a high resolution of ion beam exposure. This ion beam transfer method comes in such an approach that arranges the mask with patterns formed thereon near the wafer to thereby apply a large-diameter ion beam to the mask so that the transmitted ion beam may transfer these patterns or a reduction-projecting exposure approach that applies the ion beam to a five-fold or ten-fold sized mask to thereby perform reduction-projecting exposure of patterns onto the wafer.
The above-mentioned electron beam drawing technology uses two types of masks in batch exposure whereby circuit patterns are collectively projected to the wafer: a stencil mask having holes therein through which the electron beam passes to draw circuit patterns and a membrane type mask having a membrane for blocking the electron beam to do so.
In the case of the stencil mask, any region surrounded entirely by mask holes cannot have a portion thereof to support itself, so that such the stencil mask cannot be manufactured, which is hereinafter referred to as a donut problem. On the other hand, in a region surrounded largely by mask holes except a slight peripheral supporting portion thereof, as the portion entirely surrounded by the mask holes is much larger than the supporting portion, the slight peripheral supporting portion has a lower strength, so that when the transfer mask is made, this inner portion may be warped or deformed, which is hereinafter called a leaf problem. With this, to avoid such the donut problem and the leaf problem during manufacturing of transfer masks for drawing patterns, the mask must be checked to detect such problems manually or by use of pattern continuity so that any regions having thus detected problems may undergo application of the membrane type mask or division of patterns.
Manual detection, however, suffers from a problem of possibly creating large-scale pattern defects due to human error. The method of detecting isolated patterns by checking pattern continuity, on the other hand, suffers from a problem that it can detect only such regions that have the donut problem, so that it needs to use a separate program for the leaf problem.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the invention to provide a drawing pattern verifying method for verifying drawing patterns created on a stencil mask that can use a same algorithm to detect patterns suffering from a donut problem or a leaf problem.
According to an aspect of the present invention, there is provided a drawing pattern verifying method for verifying a drawing pattern to be formed on a stencil mask used in electron beam exposure or ion beam exposure, including steps of:
extracting the drawing pattern from device designing data;
dividing a region in which the extracted drawing pattern is arranged except mask holes into a plurality of portions;
setting to each of divided portions a variable of a plurality of kinds of variables which are determined based on likelihood of defectiveness of the portions; and
reviewing a specific variable of the portion based on likelihood of defectiveness thereof.
With the foregoing aspect, since the region except mask holes providing openings in an area for arranging the drawing pattern therein is divided into a plurality of portions so that each of these divided portions may have the variable set thereto based on its own defect occurrence likelihood, such the portion that has the specific variable which is set finally thereto when these variables are reviewed can be identified to be a defective portion, thus previously detecting the region subject to pattern defect occurrence.
In the foregoing aspect, a first preferable mode is one wherein the reviewing step includes steps of:
further dividing the portion with the specific variable into the plurality of portions; and
setting to each of the portions the variable which is determined based on likelihood of defectiveness thereof; and the further dividing step and the setting step are repeated once or a plurality of times.
With the first preferable mode, if the portion of the specific variable cannot be specified as a pattern occurrence portion when it is reviewed, the variable can be reset to verify even more complicated drawing patterns of the portion.
Also, a second preferable mode is one wherein the portion of a finally set specific variable is a first defective portion entirely surrounded by mask holes and/or a second defective portion partially surrounded by mask holes.
With the second preferable mode, it is possible to extract both the first defective portion which provides the donut problem and the second defective portion which provides the leaf problem, by using a same algorithm.
Also, a third preferable mode is one wherein the variable setting step specifically sets variables a={a0}, {a1}, {a2} (where, a0‡a1‡a2) according to rules, the rules including:
a first rule for setting to a third portion an inner portion surrounded by straight lines which are in contact with the mask hole nearest to the region arranged in the drawing pattern and which are parallel with sides of the region and also setting an outside of the third portion to variable {0}, mask holes to variable {a2}, and remaining to variable {a1};
a second rule for performing first scanning on
Ahmed Samir
NEC Electronics Corporation
Sughrue & Mion, PLLC
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