DRAM with sub data lines and match lines for test

Details DRAM with sub data lines and match lines for test DRAM with sub data lines and match lines for test

1994-05-20

1995-05-23

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

36518905, 365208, G11C 506, G11C 700

Patent

active

054187370

ABSTRACT:
A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

REFERENCES:
patent: 4807194 (1989-02-01), Yamada et al.
patent: 4943944 (1990-07-01), Sakui et al.
patent: 4947377 (1990-08-01), Hannai

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