DRAM with reduced leakage current

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

365222, 365226, G11C 1300

Patent

active

057516537

ABSTRACT:
A DRAM with reduced leakage current includes at least two line driving means for transmitting high potential to a line selected by an address signal externally input; a main power line for transmitting a power source voltage externally supplied; secondary power lines for transmitting the power source voltage to the respective line driving means; switching means respectively connected between the main power line and secondary power lines; block selection means for outputting a signal where two block selection addresses are logically combined, to each of the line driving means, in order to select and operate one of the line driving means; and switching control means for outputting a signal which controls each of the switching means through the logical combination of the output signal of the block selection means and a refresh operation mode signal.

REFERENCES:
patent: 5297098 (1994-03-01), Nakatani
patent: 5590082 (1996-12-01), Abe

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