Dram with polysi bit lines and added junction capacitance

Details Dram with polysi bit lines and added junction capacitance Dram with polysi bit lines and added junction capacitance

1983-12-29

1985-11-05

Larkins, William D.

357 41, 357 59, H01L 2704, G11C 1140

Patent

active

045517410

ABSTRACT:
A semiconductor memory device having two layers of polycrystal silicon and having an insulated gate field effect transistor as a fundamental element including by using a first layer of polycrystalline silicon serving as an electrode of a capacitor and a bit line and a second layer of polycrystalline silicon serving as a gate electrode of the transistor.

REFERENCES:
patent: 3810125 (1974-05-01), Stein
patent: 4062037 (1977-12-01), Togei et al.
patent: 4163243 (1979-07-01), Kamins
patent: 4240092 (1980-12-01), Kuo
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4262298 (1981-04-01), Tuan et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4334236 (1982-06-01), Hoffman et al.
patent: 4392210 (1983-07-01), Chan
Forlino et al., IBM Tech. Discl. Bulletin, vol. 20, No. 2, Jul. 1977, pp. 539-540.
IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb. 1979, pp. 3828-3831, Rideout.
IEEE Transactions on Electron Devices, vol. ED-26, No. 6, Jun. 1979, p. 846, Rideout.

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