DRAM with intermediate storage cache and separate read and...

Details DRAM with intermediate storage cache and separate read and... DRAM with intermediate storage cache and separate read and...

1999-01-05

2001-01-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S230010

Reexamination Certificate

active

06172893

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory structures and in particular the present invention relates to dynamic random access memory (DRAM) devices with intermediate storage, or cache, and separate read and write input/output (I/O) data paths.
BACKGROUND OF THE INVENTION
The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design and in particular to the performance of computer memory.
Computer processors and memories, however, have not pursued the same pace of development through the years. Memories are generally not able to deliver enough response speed to processors. Different approaches have been taken to reduce the gap in speed between the processors and memories. One such approach is the concept of memory hierarchy. A memory hierarchy comprises a number of different memory levels, sizes and speeds. Small amounts of fast cache memory, usually static random access memory (SRAM), are utilized in or near the processor for data that is frequently accessed, such as program instructions. The cache memory reduces the need to access main memory by temporarily storing this frequently accessed data. More space-efficient, but slower, dynamic random access memory (DRAM) can then be utilized downstream from the cache memory. This approach has been augmented by the combination of some sort of cache memory and main memory in a single memory device.
Another approach is to improve the internal response time of the memory itself. At one time, the most common version of DRAM was Fast Page Mode (FPM) DRAM. The capabilities of FPM DRAM lag far behind today's processor speeds. Extended Data-Out (EDO) DRAM was an improvement on FPM DRAM, improving page read cycle times. The primary differences between EDO DRAM and FPM DRAM is that EDO DRAM does not turn off the output drivers when CAS# (column address strobe complement) goes HIGH, and data is valid on the falling edge of CAS# such that the edge can be used to strobe data.
Synchronous DRAM (SDRAM) was a further improvement to dynamic memory devices. SDRAM added a clocked synchronous interface, multiple internal bank arrays and programmable burst inputs and outputs. Double Data Rate (DDR) DRAM allowed data clocking on both clock edges and added a return clock. Despite these advances, SDRAM and DDR are still less than optimal to support current computer processors.
One effort to increase the capabilities of DRAM is SyncLink Dynamic Random Access Memory (SLDRAM). SLDRAM is designed to be a general purpose high performance DRAM and the protocol is targeted to be formalized as an open standard by IEEE (Institute of Electrical and Electronics Engineers, Inc.). As of the date of filing, the latest revision of the proposed IEEE standard is draft 0.99 of IEEE P1596.7-199X,
Draft Standard for a High-Speed Memory Interface
(
SyncLink
), dated Oct. 14, 1996.
FIGS. 1A and 1B
combined are a functional block diagram of an existing memory device
10
incorporating the features previously described. The memory device
10
is depicted as a 144M SLDRAM (i.e., an SLDRAM having 144×2
20
bits of memory), although the discussion is generally applicable to other sizes, configurations and types of memory. For additional background on SLDRAM of the type depicted in
FIGS. 1A and 1B
, please refer to the SLDRAM, Inc. document CORP400.P65, SLD4M18DR400, 4 MEG×18 SLDRAM, revision Jul. 9, 1998, which is incorporated herein by reference.
The memory device
10
includes bank memory arrays
22
which contain memory cells organized in rows and columns for storing data. Bank memory arrays
22
are depicted as eight bank memory arrays, bank0 through bank7. In memory device
10
, each bank memory array
22
is organized internally as 2048 rows by 128 columns by 72 bits. Those skilled in the art will recognize that different choices for the number of banks, rows and columns, and the bit width, are possible without altering the fundamental operation of the memory devices described herein.
An external differential command clock (CCLK and CCLK#) signal is provided to clock dividers and delays
20
to generate clock signals ICLK (internal command clock), RCLK (read clock), WCLK (write clock) and other internal clock signals. Command input signals are effectively sampled at each crossing of internally delayed versions of CCLK/CCLK#.
A FLAG signal is supplied to command and address capture
24
to indicate that a valid request packet is available on pins CA
0
-CA
9
. Pins CA
0
-CA
9
supply the address and command bits and may collectively be referred to as the command link. Command decoder and sequencer
26
acts to place the control logic in a particular command operation sequence according to the request packet received at command and address capture
24
. Command decoder and sequencer
26
controls the various circuitry of memory device
10
based on decoded commands, such as during controlled reads to or writes from bank memory arrays
22
. During write transfer operations, data is supplied to memory device
10
via input/output pins DQ
0
-DQ
17
. During read transfer operations, data is clocked out of memory device
10
via input/output pins DQ
0
-DQ
17
. The DQ pins can collectively (when looking external of the device) or individually (when looking internal to the device) be referred to as data links. For a read access, differential data clocks (DCLK
0
/DCLK
0
# and DCLK
1
/DCLK
1
#) are clocked out of memory device
10
via input/output pins DCLK
0
, DCLK
0
#, DCLK
1
and DCLK
1
#. For a write access, differential data clocks (DCLK
0
/DCLK
0
# and DCLK
1
/DCLK
1
#) are driven externally, e.g. by a memory controller (not shown), and provided to memory device
10
via input/output pins DCLK
0
, DCLK
0
#, DCLK
1
and DCLK
1
#.
Power-up and initialization functions of the memory device
10
are conducted in the conventional manner. Moreover, refresh functions of the memory device
10
are provided in the known manner employing a refresh counter
38
to refresh the memory arrays.
During a bank access command, address sequencer
28
generates a value representing the address of the selected bank memory array
22
, as indicated by bank address bits on input pins CA
0
-CA
9
, and latches it in bank address register
44
. Address sequencer
28
further generates a value representing a row address of the selected bank memory array
22
, as indicated by row address bits on input pins CA
0
-CA
9
, and latches it in a row address register
42
. Address sequencer
28
still further generates a value representing a column address, as indicated by column address bits on input pins CA
0
-CA
9
, and latches it in column select
62
.
The latched row address is provided to a row multiplexer
46
which provides a row address to predecoder
48
to be provided to bank row selects
52
. In addition, bank address register
44
provides the latched bank address to bank control logic
54
which in turn provides a bank address to bank row selects
52
. In response to the bank address and row address, bank row selects
52
activate the desired row of the desired memory bank for processing, to thereby activate the corresponding row of memory cells. Bank row selects
52
generally have a one-tone relationship with bank memory arrays
22
.
In the memory device
10
of FIGS. and
1
B, column select
62
activates 72 of the 128×72 (number of columns x bit width) lines provided to sense amplifiers and I/O gating circuit
66
, the number of lines activated corresponding to the bit width of the device. The lines provided to sense amplifiers and I/O gating circuit
66
represent bidirectional data paths. As used herein, paths will generally describe transmission lines internal to a memory device, while links will be used to describe lines or ports generally designed for transmission between a memory device and an external device. Sense amplifiers associated with bank memory arrays
22
operate in a manner known in

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