DRAM with improved poly-to-poly capacitor

Details DRAM with improved poly-to-poly capacitor DRAM with improved poly-to-poly capacitor

1991-02-27

1992-03-24

Jackson, Jr., Jerome

357 51, 357 54, H01L 2968

Patent

active

050981927

ABSTRACT:
The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide
itride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

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patent: 4922312 (1990-05-01), Coleman et al.
Ohta et al., IEEE Trans. on Electronic Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1352-1358.
Ohta et al., IEEE Trans. on Electronic Devices, vol. ED-29, No. 3, Mar., 1982, pp. 368-376.
Koyanagi et al., IEEE J. of Solid State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 661-666.
Koyanagi et al., Proc. 10th Conf. on solid State Devices, Jap. J. App. Phys., vol. 18 (1979) Supp. 18-1, pp. 35-42.
Smith, IBM Tech. Disc. Bull, vol. 15, No. 12, May 1973, pp. 3585-3586.

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