DRAM which uses MISFETS in the peripheral circuit

Details DRAM which uses MISFETS in the peripheral circuit DRAM which uses MISFETS in the peripheral circuit

1989-04-25

1991-06-18

James, Andrew J.

357 231, 357 235, 357 236, 357 2314, 357 2315, 357 40, 357 41, 357 45, 357 49, 357 51, 357 59, H01L 2934, H01L 2701, H01L 2900, H01L 2978

Patent

active

050253018

ABSTRACT:
A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device. In addition, it is possible to lower the resistance of the gate electrode of the second field-effect transistor and to thereby increase the operating speed of the device. Since the first and second field-effect transistors can be formed on a semiconductor substrate having no damage generated thereto, it is possible to increase the dielectric strength of the gate insulator film and to thereby improve the electrical reliability of the device.

REFERENCES:
patent: 4385308 (1983-05-01), Uchida et al.
patent: 4451841 (1984-05-01), Hori et al.
patent: 4475964 (1984-10-01), Ariizumi et al.
patent: 4511911 (1985-04-01), Kenny
patent: 4536941 (1985-08-01), Kuo et al.
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4586238 (1986-05-01), Yatsuda et al.
patent: 4628590 (1986-12-01), Udo et al.
patent: 4646426 (1987-03-01), Sasaki
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4688064 (1987-08-01), Ogura et al.
patent: 4748492 (1988-05-01), Iwase et al.
patent: 4755864 (1988-07-01), Ariizumi et al.
patent: 4803534 (1989-02-01), Koike et al.
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4833647 (1989-05-01), Maeda et al.
patent: 4841481 (1989-06-01), Ikeda et al.
patent: 4845539 (1989-06-01), Inoue
patent: 4845544 (1989-06-01), Shimizu
patent: 4855801 (1989-08-01), Kuesters
patent: 4873559 (1989-10-01), Shimizu et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, pp. 86-87.

Affiliated with

Also associated with

Rating

DRAM which uses MISFETS in the peripheral circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM which uses MISFETS in the peripheral circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM which uses MISFETS in the peripheral circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-148460