DRAM technology of buried plate formation of bottle-shaped...

Details DRAM technology of buried plate formation of bottle-shaped... DRAM technology of buried plate formation of bottle-shaped...

2000-04-19

2002-04-02

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S386000, C438S249000

Reexamination Certificate

active

06365485

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a novel method for making buried layers as the first part of the process of making sub-micron-sized deep trench capacitors. More specifically, the present invention relates to a novel method for making a buried layer for use as a conductive plate in a deep trench capacitor, wherein the final deep trench capacitor contains a pair of conductive plates separated by a dielectric layer to serve as a storage mode as part of a sub-micron-sized semiconductor device. The method disclosed in the present invention enables the subsequent steps of forming the second conductive plate in the deep trench capacitor to be greatly simplified by eliminating and/or simplifying many of the complicated steps required in the conventional processes, while improving the integrity of the resultant deep trench capacitor and allowing the storage capacity of the deep trench capacitor to remain the same or even enhanced. The method of the present invention is most advantageous for forming buried plates in bottle-shaped deep trench capacitors which have an enlarged diameter, or more generally speaking, with an enlarged circumference or cross-sectional area in the bottom portion thereof. However, the method of the present invention can also be advantageously utilized for forming buried plates for conventional deep trench capacitors.
BACKGROUND OF THE INVENTION
A capacitor comprises a dielectric layer sandwiched by a pair of spaced conducting plates. There are two basic types of capacitors provided in a semiconductor device, for example, dynamic random access memory or DRAM: the crown-type capacitors and the deep-trench type capacitors. As the trend in the fabrication of semiconductor devices is toward ever-increasing density of circuit components that can be tightly packed per unit area, there are great demands to develop technologies that can reduce the surface area to be taken by individual circuit components. As a result, deep trench technologies have been developed which result in structures, particularly large area capacitors, that are vertically oriented with respect to the plane of the substrate surface.
A deep trench capacitor typically comprises a dielectric layer formed on the sidewalls of a deep trench, which is formed into and surrounded by a highly doped buried plate (which constitutes the first conducting plate), and a highly doped poly fill (which constitutes the second conducting plate), which fills the deep trench. The dielectric layer separates the first and the second conducting plates. The capacitance of the deep trench capacitor is determined by the total sidewall surface of the trench, which, in turn, is determined by the diameter, or more specifically the circumference, of the deep trench. As the semiconductor fabricating technology moves into the sub-micron or even deep sub-micron range, it is increasingly recognized that the present technology for making deep trench capacitors may be inadequate. For deep sub-micron semiconductor devices, a deep trench can have a length-to-diameter aspect ratio of 35:1 or even greater. With current technology, the diameter (or width or circumference) of the trench generally decreases with depth. Such a tapered cross-sectional area causes a significant decrease in the overall sidewall surface of the trench, and, consequently, the capacitance provided by the deep trench capacitor. This problem is expected to become even more profound as we move into the next generation of ULSI fabrication technologies that are characterized with critical dimensions of 0.15-micron or even finer.
In the conventional process for making deep trenches, a pad oxide layer
102
and a hard mask
104
are first formed on a substrate, then a deep trench
106
is formed with the aid of the hard mask
104
, as shown in FIG.
1
A.
FIG. 1B
shows that a doped dielectric layer
112
is formed on the side wall of the deep trench
106
. The deep trench
106
is then partially filled with a photoresist
1
14
in the lower portion thereof, leaving the doped dielectric layer in the upper portion of the deep trench exposed. The exposed doped dielectric layer is removed by etching, followed by filling the deep trench with a cap oxide, such as cap TEOS. Thereafter, the cap oxide is recessed (etching/deposition/etching) to form an oxide collar
116
, causing the photoresist
114
to be exposed. This is shown in FIG.
1
C.
After the photoresist
114
is removed, the substrate
100
is subjected to a thermal process to pause the impurities in the doped dielectric layer to diffuse into the substrate to form a doped zone
118
. The doped zone, or buried layer, serves as the first conductive plate for the deep trench capacitor. This is shown in FIG.
1
D.
The conventional processes involve repeated applications of chemical vapor deposition and recessing (i.e., replacing one oxide layer with another). As described in a co-pending application filed on the same date and the content thereof is incorporated herein by reference, if the conventional technology is applied to form a deep trench capacitor, the resultant bottle-shaped deep trench capacitor typically contains a second conducting plate which is made of three conducting layers. All these three layers can be made of the same material and may look as if the second conducting plate contains only an integrated layer. However, it is important to note that, due to the process steps involved, the second conducting plate typically contains conducting layers that are formed in three separate stages. The second conducting layer is formed after the formation of, in the sequence, the collar oxide and the first conducting layer. The third conducting layer, which is in contact with the semiconductive substrate, is formed after the removal of part of the collar oxide and the etching-off of corresponding part of the second conducting layer. Thus, with the conducting layers alone, the conventional processes involve at least three cycles of deposition and controlled etching. It may be possible to reduce the number of deposition/recessing/etching cycles involved in the formation of the conductive layers, but this may result in other process complexities. Furthermore, the dependence on the collar oxide to perform selected doping may cause a shorting problem in the sub-micron-sized deep trench capacitors.
In order to meet the consumers' demand and expectation of continual lowered price of electronic components, it is necessary to find ways that can significantly simplify the semiconductor fabrication process so as to reduce the manufacturing cost. This is particularly important for the fabrication of some of the most common devices such as DRAM. Equally important is the need to improve the integrity of the product, so as to minimize the failure rate and further improve the overall production cost.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop an improved process for the manufacturing of bottle-shaped deep trench capacitors which will reduce the fabrication cost while maintaining or even improving product performance and yield rate. More specifically, the primary object of the present invention is to develop an improved process for making buried plates used in the deep trench capacitors which minimizes the number of deposition/recessing/etching cycles required for the manufacturing of bottle-shaped deep trench capacitors without adversely affecting the performance of the resultant product. In fact, the modifications made in the process of the present invention actually improve the integrity of the bottle-shaped deep trench capacitor, resulting in not only cost savings but also increased product yield.
The process disclosed in the present invention is actually a port of an overall novel process for the fabrication of bottle-shaped deep trench capacitors. To ensure a continuity of this disclosure, the overall process for fabricating the bottle-shaped deep trench capacitors is summarized below which includes the following main steps:
(1) Forming a pad oxide layer and a hard

Affiliated with

Also associated with

Rating

DRAM technology of buried plate formation of bottle-shaped... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM technology of buried plate formation of bottle-shaped..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM technology of buried plate formation of bottle-shaped... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2891198