DRAM stacked capacitor fabrication process

Details DRAM stacked capacitor fabrication process DRAM stacked capacitor fabrication process

1992-03-06

1993-11-16

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437200, 437233, 437919, H01L 2170

Patent

active

052623432

ABSTRACT:
This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.

REFERENCES:
patent: 4495219 (1985-01-01), Kato et al.
patent: 4951175 (1990-08-01), Kurosawa
patent: 4970564 (1990-11-01), Kimura et al.
"A Ferroelectric Dram Cell for High-Density NVRAMS'S" by R. Moazzami et al., 1990 IEEE Electron Device Letters, Oct. 1990.
L. Manchamda, "Yitrium oxide/silicon dioxide: A new dielectric structure for VLSI/ULSI structure" IEEE Electron Dev. Letters vol. 9, Apr. 11, 1988, p. 180.

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