DRAM process with improved polysilicon-to-polysilicon capacitor

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357 54, H01L 2978

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active

049223127

ABSTRACT:
The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide
itride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

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patent: 4355374 (1982-10-01), Sakai et al.
patent: 4455568 (1984-06-01), Shiota
Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM," Proc. of the 10th Conf. on Solid State Devices, Tokyo, 1978; Jap. J. of Appl. Phys., vol. 18, (1979), Suppl. 18-1, pp. 35-42.
Tolley et al., "72-K RAM Stands Up to Hard and Soft Errors," Electronics, Jun. 16, 1982, pp. 147-151.
Jolly et al., "A Dynamic RAM Cell in Recrystallized Polysilicon," IEEE Elec. Device Letters, vol. EDL-4, No. 1, 1/83, pp. 8-11.
Heald et al., "Multilevel Random-Access Memory Using One Trans. Per Cell," IEEE J. of S.S. Circuits, vol. SC-11, No. 4, Aug. 1976, pp. 519-527.

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