DRAM power management with self-refresh

Details DRAM power management with self-refresh DRAM power management with self-refresh

1992-03-24

1994-11-15

LaRoche, Eugene R.

Static information storage and retrieval

Powering

365222, 365227, G11C 700

Patent

active

053654870

ABSTRACT:
A DRAM furnishes power management circuits that remove power from circuits on the DRAM that are not necessary for self-refresh and that turn on and off other circuits necessary for self-refresh in timed relation to the refresh cycle. The power management circuits include a counter and simple decoder circuits that decode the binary output of the counter.

REFERENCES:
patent: 4279020 (1981-07-01), Christian et al.
patent: 4334157 (1982-08-01), White, Jr. et al.
patent: 4334295 (1982-06-01), Nagami
patent: 4653030 (1987-03-01), Tochibono et al.
patent: 4686386 (1987-08-01), Tadao
Konishi, Yasuhiro et al., "A 33-ns 4-Mb DRAM with a Battery-Backup (BBU) Mode", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1112-1116.
"4M Bit Dynamic RAM (Self Refresh, Fast Page & Byte Read/Write Modes)", MOS Integrated Circuit .mu.PD424xxxx, NEC Corporation, 1990.

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