DRAM power bus control

Details DRAM power bus control DRAM power bus control

2007-10-02

2007-10-02

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Powering

C365S222000, C365S228000, C365S206000

Reexamination Certificate

active

11347162

ABSTRACT:
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

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