Static information storage and retrieval – Powering
Reexamination Certificate
2002-08-23
2004-09-21
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Powering
C365S222000, C365S189090
Reexamination Certificate
active
06795365
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to dynamic random access memories (DRAMs). More particularly, this invention relates to power distribution on DRAMs.
A DRAM is a form of semiconductor random access memory (RAM) commonly used as main memory in computers and other electronic systems. DRAMs store information in arrays of integrated circuits that include capacitors. Because capacitors lose their charge over time, they need to be regularly recharged. This regular recharging is performed during “refresh” cycles.
DRAMs also include other circuits and devices, known as peripherals, that support memory read and write operations as well as other DRAM functions. High speed DRAMs, known as synchronous DRAMs (SDRAMs), use clocks to synchronize control and data signal transfers and include peripherals known as delay lock loop (DLL) circuits to maintain that synchronization.
DLL circuits, however, are susceptible to power and ground bus noise typically generated by the memory arrays during row activations and data reads and writes. This susceptibility can cause the DRAM to lose synchronization. Loss of synchronization causes timing problems that can result in the wrong data being read from or written to memory, thus adversely affecting data integrity throughout a computer or other system.
One known solution is to isolate the power and ground buses connected to the DLL and other synchronization control circuits from the power and ground buses connected to the DRAM arrays. This can be done by running separate power and ground buses to peripheral circuits from one set of chip power and ground input/output (I/O) pads and running separate power and ground buses to the arrays from another set of chip power and ground I/O pads. Each chip power and ground pad is connected to an external voltage. Thus, rather than have a network of power and ground buses commonly connected to all respective power and ground pads, separate and isolated power and ground buses are connected to respective subsets of the DRAM chip's power and ground pads.
Such power distribution, however, results in less available current per separate power bus, because each bus has fewer pads connected to it from which to draw current. Each power pad can supply only a limited amount of current. This can adversely affect the DRAM arrays during refresh cycles when significantly increased amounts of current are needed to recharge the capacitors. With less current available, the capacitors may not fully charge. This can decrease the time that a capacitor retains the correct stored value, thus resulting in either a loss of stored data or more frequent refresh cycles. More frequent refresh cycles result in reduced DRAM performance, because read/write operations cannot be performed during refresh cycles.
In view of the foregoing, it would be desirable to provide synchronization control circuits with power and ground busing having inconsequential, if any, noise generated by memory arrays during row activations and read/write operations while still providing the arrays with sufficient current during refresh cycles.
SUMMARY OF THE INVENTION
It is an object of this invention to provide synchronization control circuits with power and ground busing having inconsequential, if any, noise generated by memory arrays during row activations and read/write operations while still providing the arrays with sufficient current during refresh cycles.
In accordance with this invention, power distribution on DRAM chips is provided such that DLL and other peripheral circuits are supplied with power and ground substantially free of any noise generated by array row activations and read/write operations. This power and ground is supplied via dedicated power and ground pads not used by the arrays during non-refresh operations. The DRAM power distribution also supplies sufficient current to the arrays during refresh cycles via a switchable connection between array power busing and power busing connected to one or more power pads also not used by the arrays during non-refresh operations.
In a preferred embodiment of the invention, a DRAM chip has array power buses that provide a regulated voltage to the arrays, peripheral power buses that provide a regulated voltage to DLL and other peripheral circuits, and a third power bus that provides an unregulated voltage to still other peripheral circuits. The peripheral and third power buses are connected to one or more power pads other than the power pads connected to the array power buses. The power pads connected to the peripheral and third power buses can be the same. Preferably, the unregulated voltage provided by the third power bus is higher than the regulated voltages provided by the array and peripheral power buses. The DRAM chip further includes a switch that connects the array power bus to the third power bus. The switch closes for a finite period of time preferably at the start of each refresh cycle to provide additional current to the arrays. The switch opens preferably well before or at least by the end of the refresh cycle.
In a more preferred embodiment of the invention, the switch is a p-channel FET (field effect transistor) with its source connected to the third power bus and its drain connected to the array power bus. A signal pulse applied to the FET's gate turns it ON (i.e., renders it conductive) for a momentary period of time preferably at the start of each refresh cycle. The third power bus then supplies needed current through the conductive p-channel FET to the DRAM arrays. The DLL and other peripheral circuits are not affected by this because no reading or writing of data occurs during refresh cycles, thus the temporary connection between the array and third power bus has no adverse affect on synchronization or data integrity.
The invention advantageously provides DLL and other peripheral circuits with noise isolation during DRAM row activations and data reads and writes while providing increased current during at least a portion of each DRAM array refresh cycle.
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Fish & Neave
Micro)n Technology, Inc.
Nguyen Viet Q.
Tuma Garry J.
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