Dram nonvolatizer

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36496579, 3649649, 3649485, 364968, 365222, 365228, 365229, G06F 1216, G11C 1140

Patent

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049775375

ABSTRACT:
A nonvolatile memory subsystem includes DRAMs and a battery-backed controller chip. The controller chip monitors the system power supply level to ascertain power fault conditions. When a power fault is detected, the controller provides the DRAMs with both a regulated supply voltage and appropriately timed refresh signals.
After the system power supply has returned to specification, the controller continues to generate refresh control signals until the commands it to stop.

REFERENCES:
patent: 4015219 (1977-03-01), Kawagoe et al.
patent: 4313180 (1982-01-01), Mochizuki et al.
patent: 4317054 (1982-02-01), Caruso et al.
patent: 4384350 (1983-05-01), Lee et al.
patent: 4406013 (1983-08-01), Reese et al.
patent: 4412284 (1983-10-01), Kerforne et al.
patent: 4594565 (1986-06-01), Barrerras
patent: 4607238 (1986-08-01), Kohsiek
patent: 4628457 (1986-12-01), Manduley
Motorola Memory Data Manual, 1982, pp. 2-72.
Curtis, W., Silicon Complication, IEEE Potentials, May 1986, pp. 27-29.
Application Note from National Semiconductor, published in 1977, reprinted in Analog Integrated Circuits (ed. Grebene 1978) pp. 173-178.
Brokaw, "A Simple Three-Terminal IC Bandgap Reference," 9 J. Solid State Circuits 388 (Dec. 1974), reprinted in Analog Integrated Circuits, (ed. Grebene 1978) pp. 167-172.
Motorola Application Note, from Pages 4:69ff of the M6800 Microprocessor Application Manual (1975).

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