1991-05-14
1994-05-17
Atkinson, Charles E.
Excavating
371 401, 395275, 395425, G06F 1110
Patent
active
053136241
ABSTRACT:
The present invention provides a system for supporting one or more memory requestors (CPU's and I/O DMA) accessing a plurality of DRAM memory banks. The present invention is a multiplexer that functions as a 16-bit slice of the interface between the CPU and a 64-bit slice of DRAM memory array. The invention includes an error correction (ECC) module, a 64-bit DRAM I/O channel, an 8-bit ECC "syndrome" I/O channel and an 8-bit slice of a DMA bus I/O channel. In a write operation, the CPU transmits data through the I/O channel to write the data to the DRAM. Each word is routed by the four-way multiplexer to one of the four memory registers. When the four registers have been filled with data words, the words are assembled into a multiple word burst and sent to the DRAM bank. The data is also passed through an error correction module. For a read operation, DRAM data is latched into the CPU register and transported to the CPU while the DRAM is potentially being accessed for another memory read.
REFERENCES:
patent: 4644463 (1987-02-01), Hotchkin et al.
patent: 4688166 (1987-08-01), Schneider
patent: 4951246 (1990-08-01), Fromm et al.
patent: 4953103 (1990-08-01), Suzuki
patent: 4965801 (1990-10-01), DuLac
patent: 5159679 (1992-10-01), Culley
patent: 5163132 (1992-11-01), DuLac et al.
Harriman Guy
Ross Mark
Atkinson Charles E.
Next Computer, Inc.
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