DRAM memory cell having a horizontal SOI transfer device dispose

Details DRAM memory cell having a horizontal SOI transfer device dispose DRAM memory cell having a horizontal SOI transfer device dispose

1991-04-30

1991-10-08

Wojciechowicz, Edward J.

Fishing, trapping, and vermin destroying

357 237, 357 41, 357 50, 357 51, 357 55, 357 59, 357 68, 437 29, 437 49, 437 84, 437913, 437919, H01L 2978, H01L 21265

Patent

active

050558986

ABSTRACT:
A semiconductor memory cell, and methods of fabricating same, that includes a substrate (10) and a plurality of trench capacitors (12) formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator (SOI) region includes a silicon layer (16) that overlies an insulator (14). The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline (20), for forming a gate node of an access transistor (1), to a second electrode, or bitline (32), for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure (11, 13) for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.

REFERENCES:
patent: 4507171 (1985-03-01), Bhatia et al.
patent: 4728623 (1988-03-01), Lu et al.
patent: 4799990 (1989-01-01), Kerbaugh et al.
patent: 4816884 (1989-03-01), Hwang et al.
patent: 4958318 (1990-09-01), Harari
"Process for Making Contacts or Vias to High Density Fine Lines", IBM Tech. Discl. Bulletin, vol. 30, No. 8, Jan. 1988.
"Si-Gate CMOS Devices on a Si/CaF.sub.2 /Si Structure", IEEE Transactions on Electron Devices, vol. ED-34, No. 11, Nov. 1987, by H. Onoda et al.

Affiliated with

Also associated with

Rating

DRAM memory cell having a horizontal SOI transfer device dispose does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM memory cell having a horizontal SOI transfer device dispose, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM memory cell having a horizontal SOI transfer device dispose will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-260525