DRAM interface circuits having enhanced skew, slew rate and...

Details DRAM interface circuits having enhanced skew, slew rate and... DRAM interface circuits having enhanced skew, slew rate and...

2006-07-18

2006-07-18

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C711S105000, C711S167000

Reexamination Certificate

active

07079446

ABSTRACT:
Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

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