Dram interface adapter circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307475, 365193, H03K 1920, H03K 190175, G11C 700

Patent

active

052412229

ABSTRACT:
The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit. The interface adapter circuit can also convert write nd column address timing signals and low and high byte write signals into the two sets responsive to a selection signal.

REFERENCES:
patent: 4649511 (1987-03-01), Gdula
patent: 4797850 (1989-01-01), Amitai
patent: 5005157 (1991-04-01), Catlin

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