DRAM having output control circuit

Details DRAM having output control circuit DRAM having output control circuit

1996-01-18

1997-03-04

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523008, 365194, G11C 706

Patent

active

056086881

ABSTRACT:
A DRAM having an output control circuit for preventing undesired data from being outputted from the DRAM when an address is transited before a column address strobe signal is latched during DRAM read operation, and allowing desired data to be outputted from the DRAM when a global input/output data signal is precharged after the column address strobe signal is latched.

REFERENCES:
patent: 5268873 (1993-12-01), Suzuki
patent: 5331595 (1994-07-01), Inoue
patent: 5345421 (1994-09-01), Iwamura et al.

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