DRAM having each memory cell storing plural bit data

Details DRAM having each memory cell storing plural bit data DRAM having each memory cell storing plural bit data

1999-04-16

2000-11-21

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365149, 365205, 36523003, G11C 506

Patent

active

061512370

ABSTRACT:
In a dynamic type semiconductor memory device having a classified bit line structure, a feedback capacitor is provided between sub-bit lines and main bit lines of a sub-sense amplifier. A voltage difference read out on the sub-bit lines is transferred to the main bit lines, the read out voltage difference is amplified by a main sense amplifier, and data of superordinate bits is read out. At the same time, the data on said main bit lines is feed-backed to the sub-bit lines through the capacitor. Thereafter, a reading operation from the sub-bit lines to the main bit lines is performed again, thereby enabling a reading operation for data of subordinate bits. Thus, in a dynamic type semiconductor memory device having a conventional memory cell structure, data for two bits can be stored in one memory cell.

REFERENCES:
patent: 5274598 (1993-12-01), Fujii et al.
patent: 5353255 (1994-10-01), Komuro
patent: 5430627 (1995-07-01), Kuwabara
patent: 5652726 (1997-07-01), Tsukude et al.
patent: 5661686 (1997-08-01), Gotou

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