Static information storage and retrieval – Powering
Reexamination Certificate
2000-02-17
2002-02-26
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Powering
C365S227000, C365S228000, C365S189110
Reexamination Certificate
active
06351426
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a power supply voltage lowering circuit for lowering a power supply voltage from the external and supplying the lowered voltage to an internal circuit, and is particularly suitable for a logic LSI such as a microprocessor or DRAM.
2. Description of the Related Art
In a semiconductor integrated circuit device such as a DRAM, since the withstand voltage of the gate insulative film of a MOS transistor is lowered and the resistance to hot carriers is degraded when it is further miniaturized, it becomes necessary to lower the power supply voltage. However, since the whole system must be changed in order to lower the power supply voltage itself which is supplied to the chip, it becomes a common practice to hold the voltage of the system at 5V as in the conventional case and use a voltage obtained by lowering the power supply voltage supplied from the exterior in the chip in the case of 16-Mbit DRAM.
On the other hand, in the case of 64-Mbit DRAM, the power supply voltage V
CC
for the whole system is lowered to 3.3V, but the power supply voltage lowering circuit is widely used in the chip. The reason is to make the power consumption as small as possible or enlarge the operation margin of the internal circuit and input characteristic for the power supply voltage V
CC
and is different from the demand for the 16-Mbit DRAM, but it is considered that the power supply voltage lowering circuit will be widely used not only in the DRAM but also in the semiconductor integrated circuit device.
As the conventional power supply voltage lowering circuit, a feedback type circuit including a P-channel MOS transistor as shown in
FIG. 1 and a
source follower type circuit including an N-channel MOS transistor as shown in
FIG. 2
are known. The basic construction of the former power supply voltage lowering circuit is described in, for example, 1986 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 272 and 273, Furuyama et al. “An Experimental 4Mb CMOS DRAM”.
The power supply voltage lowering circuit shown in
FIG. 1
creates an internal power supply voltage V
DD
by lowering a power supply voltage V
CC
supplied from the exterior and includes P-channel MOS transistors T
1
to T
4
, N-channel MOS transistors T
5
to T
8
, and resistors R
1
, R
2
. The sources of the MOS transistors T
5
and T
6
are connected together and the MOS transistors T
1
and T
2
which are connected in a current mirror configuration are connected between the power supply node V
CC
and the respective drains of the MOS transistors T
5
and T
6
. The drain-source paths of the MOS transistors T
7
, T
8
are serially connected between the source common connection node of the MOS transistors T
5
, T
6
and the ground node GND. The drain of the MOS transistor T
3
is connected to the drain common connection node of the MOS transistors T
2
, T
6
and the source thereof is connected to the power supply node V
CC
. Further, the gate of the MOS transistor T
4
is connected to the drain common connection node of the MOS transistors T
2
, T
6
and the source thereof is connected to the power supply node V
CC
. The resistors R
1
and R
2
are serially connected between the drain of the MOS transistor T
4
and the ground node GND. The gate of the MOS transistor T
5
is connected to the connection node between the resistors R
1
and R
2
and is applied with a potential V
R
created by dividing an output potential V
DD
.
The gate of the MOS transistor T
6
is applied with a reference potential V
REF
and the gates of the MOS transistors T
3
, T
7
are supplied with an operation control signal ACT for determining whether the power supply voltage lowering circuit should be operated or not. The operation control signal ACT is set at a high level when the power supply voltage lowering circuit is operated and is set to a low level when the operation thereof is interrupted, and when the power supply voltage lowering circuit is used in a DRAM, for example, the signal ACT is set at a high level in the operative mode and set at a low level in the standby mode. The gate of the MOS transistor T
8
is supplied with a signal VCON for driving the MOS transistor T
8
as a constant current source. The signal VCON is a constant potential set at an intermediate level between the power supply potential V
CC
and the ground potential GND. The internal power supply potential V
DD
obtained by lowering the power supply potential V
CC
is derived from the connection node between the drain of the MOS transistor T
4
and the resistor R
1
.
The circuit shown in
FIG. 1
keeps the output potential V
DD
at a constant level by comparing the potential V
R
with the reference potential V
REF
in the CMOS current mirror type comparing circuit constructed by the MOS transistors T
1
, T
2
, T
5
to T
8
and controlling the MOS transistor T
4
according to the result of comparison. In a case where the internal power supply potential V
DD
is lower than a preset potential, that is, when V
R
<V
REF
, the MOS transistor T
4
is set to the ON state to raise the output potential V
DD
, and when V
R
>V
REF
, the MOS transistor T
4
is set to the OFF state to lower the output potential V
DD
.
FIG. 3
shows the relation between the output potential V
DD
of the power supply voltage lowering circuit and the external power supply potential V
CC
. In
FIG. 3
, it is ideal if “V
DD
=V
CC
” when V
CC
<3.5V as indicated by a one-dot-dash line, but in practice, the driving ability of the P-channel MOS transistor T
4
is not so large since the size of the P-channel MOS transistor T
4
is limited (when it is made excessively large, the delay time in the feedback loop including the current mirror circuit in the case of “V
CC
>3.5V” becomes too long and the operation becomes unstable) and the potential applied to the gate of the MOS transistor T
4
is an output directly derived from the current mirror circuit and is not set at the GND level, and the relation of “V
DD
<V
CC
” is obtained as indicated by the solid line. Further, in the feedback type voltage lowering circuit including the P-channel MOS transistor, the feedback operation is effected and the output potential will oscillate in some condition, and therefore, fine adjustment by phase compensation, for example, is required, thereby making the circuit design difficult. In addition, since the feedback time constant is not limitlessly small, it cannot respond to a rapid variation in the internal potential and noise will be generated.
On the other hand, the power supply voltage lowering circuit of
FIG. 2
is a source follower type circuit using an N-channel MOS transistor T
10
. An internal power supply voltage V
DD
output from the source of the voltage lowering MOS transistor T
10
of N channel type is controlled to “V
PP
−V
TH
(V
TH
is a threshold voltage of the N-channel MOS transistor T
10
)” by applying a high potential V
PP
to the gate of the MOS transistor T
10
and applying an external power supply potential V
CC
to the drain thereof. Since the power supply voltage lowering circuit of source follower type using the N-channel MOS transistor T
10
has no defects of oscillation and through current which are caused in the feedback type circuit, the MOS transistor size can be made sufficiently large, the response to the internal load is good, and the circuit characteristic is excellent. Further, by dispersedly arranging the N-channel MOS transistor T
10
in the chip, degradation in the AC characteristic due to an IR drop caused by a resistance between the V
DD
generation circuit and the actual load circuit will not occur and an excellent response characteristic can be attained.
However, the power supply voltage lowering circuit of source follower type has an essential defect that the internal potential will be made significantly higher than an original preset value in a standby state in which almost no load current flows. Further, even in a
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Nguyen Viet Q.
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