DRAM for storing data in pairs of cells

Details DRAM for storing data in pairs of cells DRAM for storing data in pairs of cells

2000-08-31

2002-02-05

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S149000, C365S190000, C365S205000

Reexamination Certificate

active

06344990

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to dynamic RAM (DRAM) to store data in pairs of cells, and particularly to DRAM which, through a twin-cell structure, is able to reduce power consumption, or is able to speed up the operation. In this Specification, such DRAM is referred to as “twin-cell DRAM.”
2. Description of the Related Art
DRAM is large-capacity memory having memory cells consisting of one selection transistor (cell transistor) and one storage capacitor (cell capacitor). It is widely used as the cache memory in computers and in other applications.
In conventional DRAM, by driving a selected word line, the cell transistors connected to the word line are made conducting, cell capacitors are connected to bit lines, the bit line potential is raised or lowered according to whether there is or is not an electric charge on the cell capacitor, and this charge is read by a sense amplifier. Here in order to increase the read sensitivity, another bit line connected to the sense amplifier is used as a reference potential.
That is, in conventional DRAM, data 1's and 0's are stored by either accumulating or not accumulating electric charge in a single cell capacitor. This state is reflected in the potential of one bit line, and using the potential of the other bit line as a reference potential, the sense amplifier reads the data stored in the cell.
FIG. 9
is a drawing showing the configuration of conventional DRAM. In
FIG. 9
, sense amplifier blocks S/A
0
, S/A
1
containing sense amplifier circuits are arranged on both sides of the memory cell array MCA. Within the memory cell array MCA are arranged plural word lines WL
0
to WL
5
, and plural bit lines BL
0
, /BL
0
and BL
1
, /BL
1
intersecting with the former; at the positions of intersection are positioned memory cells MC
00
, etc. Consisting of a cell transistor and cell capacitor. The bit line pair BL
0
, /BL
0
are connected to the sense amplifier block S/A
0
, and the bit line pair BL
1
, /BL
1
is connected to the sense amplifier block S/A
1
.
Within the sense amplifier block S/A
1
are provided bit line transfer gates BLT
1
, /BLT
1
, a precharge circuit PR
1
, a sense amplifier circuit SA
1
, and a column gate CLG. The bit line transfer gates BLT
2
, /BLT
2
are connected to a bit line pair within a memory cell array on the right side, not shown.
Read operations in the conventional DRAM of
FIG. 9
are as follows. During the precharge interval, the bit line pair BL
1
, /BL
1
is precharged to a precharge level VBL by activation of an equalizing signal EQ
12
. This precharge level is normally the voltage Vii/2(Vcc/2) intermediate between the cell voltage and bit line voltage Vii(Vcc) on the H-level side, and the ground voltage on the L-level side. Next, when the word line WL
2
is selected and driven, the transistors of the memory cells MC
21
, MC
20
are made conducting, and the potentials of the bit lines BL
1
, BL
0
change according to the cell voltages. The sense amplifier SA
1
within the sense amplifier block S/A
1
is activated by the activation signals SAE, /SAE, the voltage difference between the bit lines BL
1
and /BL
1
is detected, and the bit line pair BL
1
, /BL
1
is amplified to either the power source voltage Vii(Vcc) or to ground voltage Vss by the sense amplifier SA
1
. Finally, the column gate CLG is made conducting by activation of the column select signal CL, and the voltage amplified by the sense amplifier is read to the data bus lines DB, /DB.
Presently the word line WL
2
drops, the amplified bit line potential is retained in the memory cell MC
21
, rewriting is performed, the sense amplifier is deactivated, and bit line precharge is performed.
As described above, in conventional DRAM a data
1
or
0
is stored in a single memory cell, and when the memory cell is selected, the potential of one bit line changes while the potential of the other bit line is used as a reference potential, and the stored data is read by the sense amplifier.
Because of this configuration, conventional DRAM is subject to various constraints. For example, the cell voltage in a memory cell which stores the H level must be kept at a prescribed high-voltage level higher than the reference voltage Vii/2, even when the voltage declines due to a leakage current. If the H-level cell voltage drops below this, the corresponding bit line potential can no longer be raised sufficiently, and detection by the sense amplifier becomes difficult. Hence in conventional DRAM, in order that data reading failure due to leakage current does not occur, refresh operations must be performed at prescribed time intervals.
Further, in conventional DRAM it is desirable that the word line driving potential be set higher than the H-level side cell voltage or bit line voltage by an amount equal to or greater than the cell transistor threshold voltage, in order that the H-level side cell voltage be made sufficiently high. This is because by setting the H-level side cell voltage sufficiently high, the bit line potential can be raised sufficiently during reading, and it becomes possible to read using the sense amplifier. And even if the cell voltage declines due to the leakage current, if the voltage is higher than a prescribed voltage above the bit line precharge level Vii/2, the bit line potential can be raised sufficiently, as described above.
Also, in conventional DRAM, during read operations the word line is driven at a sufficiently high level, and after drawing the charge within the memory cell onto the bit line sufficiently, it is desirable that the sense amplifier be activated. This is because in order to enable detection by the sense amplifier, the bit line potential must be raised sufficiently relative to the cell voltage H level. This operation invites slowing of operations.
The various constraints described above on the frequent refresh operation, on raising the word line to high voltage and on other operations, all invite increases in power consumption. In DRAM devices, large capacities have been achieved through advances in microminiature processing technology, but on the other hand, the drawback of large power consumption accompanying the fact that refresh operations are necessary and other circumstances, has not yet been adequately resolved. Conversely, conventional DRAM has the problem that if power consumption is reduced, operation is slowed.
As a DRAM which resolves the above problems, a twin-cell DRAM device has been proposed in which complementary data is stored in a pair of memory cells, and in reading this pair of memory cells is selected simultaneously, the complementary data read to a bit line pair, and the bit line pair is driven by a sense amplifier. For example, in Japanese Patent Publication No. S54-28252 (Great Britain Patent No. 1502334), Japanese Patent Laid-open No. S55-157194, Japanese Patent Laid-open No. S61-34790, and Japanese Patent Laid-open No. 8-222706 (U.S. Pat. No. 5,661,678) are described configurations for storing a single datum in two memory cells.
However, all of these previous methods merely describe how a single datum is simply stored in a pair of memory cells, complementary data is read to a bit line pair, and driving is performed by a sense amplifier. The twin-cell DRAM of these previous methods do result in larger operating margins for sense amplifiers, and refresh cycles can be lengthen to some extent; but problems remain, including the facts that all sense amplifiers operate simultaneously, and that the operating margin is reduced by crosstalk between neighboring bit lines.
SUMMARY OF THE INVENTION
The object of this invention is to provide a DRAM device with a novel structure, with reduced power consumption.
A separate object of this invention is to provide a DRAM device with a novel structure, which is able to lengthen refresh cycles and reduce power consumption.
In order to achieve the above objects, as one aspect of this invention, the DRAM is configured such that data to be stored is stored as complementary data in one pair of memory cells, a

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