DRAM device having cells staggered along adjacent rows and sourc

Details DRAM device having cells staggered along adjacent rows and sourc DRAM device having cells staggered along adjacent rows and sourc

1994-07-05

1995-03-07

Harvey, Jack B.

Static information storage and retrieval

Format or disposition of elements

365 63, 365 72, 365149, G11C 502, G11C 506, G11C 1124

Patent

active

053964519

ABSTRACT:
A dynamic random access memory (DRAM) device includes: a plurality of sense amplifiers; bit lines connected to the amplifiers, respectively; a first group of memory cells arranged in a row and connected to one of the bit lines; and a second group of memory cells arranged in a row and connected to the same bit line; the first and second groups being arranged side by side and adjacently to each other, shifted one from the other by a half of a memory cell pitch, and connected alternately to each other in an open bit line system.

REFERENCES:
patent: 4319342 (1982-03-01), Scheuerlein
patent: 4641166 (1987-02-01), Takemae et al.
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4651183 (1987-03-01), Lange et al.
patent: 4689770 (1987-08-01), Miyamoto et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4903344 (1990-02-01), Inoue
patent: 4974040 (1990-11-01), Taguchi et al.
patent: 5071783 (1991-12-01), Taguchi et al.
Takemae et al, Nikkei Electronics, No. 370, Jun. 3, 1985, pp. 209-231.

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